Part Number: MSP430F5438
With Timer B driven by SMCLK configured for DCO at 12 MHz, and ACLK driven from XT1 crystal at 32768 Hz, using capture/compare module block 6 with CCIS = CCI6B, trying to latch TB0R into TB0CCR6 at every falling edge of ACLK.
No joy; CCI never appears non-0 (in debugger); interrupt for TB0CCR6 capture never fires.
Manually (in debugger) toggling CCIS from 10 to 11 and back, forcing CCI source from VCC to GND and back, forces falling edge detection in CCI and TB0R value gets latched into TB0CCR6.
Plenty of evidence elsewhere (Timer A sourced from ACLK) that ACLK is running and falling edges should be available.
static void vInitializeTimerB0CCR6( void ) {
// Disable Interrupts
_DINT() ;
// run TB0R from SMCLK continuous
/* [Already done by osal_init_system()->osalTimerInit()!]
TB0CTL = TBSSEL__SMCLK + MC__CONTINUOUS + TBCLR ;
*/
// set CCR6 to latch TB0R on falling edges of ACLK
TB0CCTL6
= CAP // Capture mode
+ CCIS_1 // Capture input (trigger) select: 1 - CCIxB ( = ACLK )
+ CM_2 // Capture mode: 1 - neg. edge */
+ CCIE // Capture/compare interrupt enable
+ SCS // Capture sychronize
;
// "Setting the SCS bit to synchronize the capture signal with the timer clock is recommended."
// Enable Interrupts
_EINT() ;
}