MSP430FR59941: Maximum SPI throughput

Hi Cody,

1.Do you see this a feasible?

[Wei]Sure,it is feasible.

2.If the DMA is configured to do this transfer, are any CPU cycles required?

[Wei] DMA transferring doesn't need CPU running. You only need CPU to do the DMA initialization and DMA interrupt routine service when a DMA task is completed.

3.What the is the maximum throughput that could be achieved using the eUSCI module in SPI mode?

[Wei] You could find the maximum BITCLK clock frequency of SPI in section 5.12.8 of the device datasheet.

4.If using the DMA, how much latency should I expect from the ADC's end of conversion until the last bit is transferred out of the SPI?

[Wei] It's difficult to give a simple answer about this. I would show you the progress in this steps within MSP430. An ADC'S end of conversion, ADC IFG event, should trigger the configured DMA channel, you could configure the DMA trigger source to ADC end of conversion event, to start the the transfer. Then DMA would take approx 2 MCLK cycles to complete the transferring to SPI TX buffer. Next, SPI will send the data in TX buffer to the bus.  You could take a simple test to capture the time slot for these progresses.

Hi Cody,

I would suggest MSP430FR5739 with a 24MHz max system clock frequency as well as the SPI eUSCI input clock frequency.