MSP430I2041: Nasty Crosstalk Between A/D Channels

Hi user6131995,

The crosstalk between converters is shown in the datasheet (-120dB typ), but your results are unexpected.

We are looking into this issue, but can you help me clarifying a few things?

- It seems like you are waiting until the 4th conversion (SD24INTDLY=0), is that right?

- Are you using a TI board or your own?

- When you say ~20% crosstalk, is that over 16-bit result?

- Do you have any screenshots?

- Out of curiosity, do you get similar results after multiple conversions and/or different OSR?

Regards,

Luis R

>It seems like you are waiting until the 4th conversion (SD24INTDLY=0)

Don't you have that backwards?  I thought SD24INTDLY=0 means that
I am NOT waiting for the 4th conversion.  Anyway, I do NOT have that
bit set, because I am running continuous conversions until the end
of time so I don't care if the first 3 are wrong.  Um, maybe I don't
properly understand SD24INTDLY at all? :-)  

My understanding is that for an OSR of, say, 128, the A/D converter
would average 128 samples.  If SD24INTDLY=0 then it would take 128
samples and average them and then report the result to me in an
interrupt.  If SD24INTDLY=1 then it would take 131 samples, and then
average samples 4 thru 131 and report the result to me.  I assume
this SD24INTDLY behavior would be the same whether I was using
single conversions or continuous conversions (in the latter case,
the delay wold be unnecessary and wastful).  Do I have this wrong?

>do you get similar results after multiple conversions and/or
>different OSR?

  I am running CONTINUOUS conversions, so, yes, that is what I
would call multiple. :-)  And I get similar results for different
OSRs.

This is a homebrew board, not TI, and there are no screenshots;
the A/D conversion results are output via a serial data stream.

Okay, here is some new information:

First, I forgot to tell you something that might be very important,
which is that my three analog inputs all have a common reference
(ground).  I have this common ground connected to A0- and to A1-
and to A2- and NOT connected to anything else.  (AVSS is connected
to digital ground, but neither is connected to the common ground
of the analog signals.)

Second, I am driving this thing too hard.  Testing with an
oscilloscope reveals that I cannot achieve the data packet rate
I need (5000 packets per second) with continuous A/D conversions.
I will have to switch to single conversions (of all three
channels simultaneously), triggered each time by the timer that
tells me when it is time to transmit a new data packet.  Thus, I
will let the timer tell me when to start the A/D conversions, and
let the A/D converter ISR tell me when to send a data packet.
This should work fine, because I am willing to lower the OSR until
I can support the packet rate I need.

As an aside, I should mention that the reason I am running out of
horsepower with this chip is the fact that its "enhanced" UART
does not understand standard 9-bit data characters, so I have to
bit-bang the output data packets (at 500,000 baud).  This chip
will be very busy working for me. :-)

-eNick

Hi Nick,

A few things:

user6131995 said:

I thought SD24INTDLY=0 means that
I am NOT waiting for the 4th conversion.

It's a bit confusing, but having SD24INTDLY=0 means that you are waiting until the 4th conversion to start generating conversion interrupts:

This is generally used whenever you are starting up the ADC or whenever the SD24INCTLx register is modified (as mentioned above) to reduce error and provide better accuracy.

user6131995 said:

My understanding is that for an OSR of, say, 128, the A/D converter
would average 128 samples.  If SD24INTDLY=0 then it would take 128
samples and average them and then report the result to me in an
interrupt.  If SD24INTDLY=1 then it would take 131 samples, and then
average samples 4 thru 131 and report the result to me.  I assume
this SD24INTDLY behavior would be the same whether I was using
single conversions or continuous conversions (in the latter case,
the delay wold be unnecessary and wastful).  Do I have this wrong?

The OSR (over-sampling ratio) is defined to be the ratio of the modulator frequency to the sample frequency:

So the OSR does not define the number of samples, but the time between each sample taken. The higher the OSR, the more time (or modulation clock cycles) there will be between samples.

When SD24INTDLY = 0, you will receive conversion interrupts after the 4th conversion until you stop sampling. The OSR does not define the number of samples you will take.

user6131995 said:

>do you get similar results after multiple conversions

Assuming that you wait 4 conversions before triggering conversion interrupts (SD24INTDLY = 0) after start up, yes, you should get similar results after multiple conversions. 

user6131995 said:

>different OSR?

Different OSRs should all give you similar results, but generally a higher OSR will provide better accuracy and reduce noise in your results.

Regarding the original cross-talk issue:

I am wondering if it's possible that there may be something in your circuit varying the common mode voltage, and making it looks like cross-talk. A few tests that might be worth trying:

1. Are you able to connect the grounded ADC channels to AVSS? This could be worth testing.

2. Can you short the positive and negative terminals of one of the ADC channels together and see if that channel still sees the same crosstalk as before?

Thanks,

Mitch

>SD24INTDLY=0 means that you are waiting until the 4th conversion

  I thought that was simply a documentation error!  It seems totally
BACKWARDS to me, but I'm gonna believe you. :-)  Besides, that would
only affect accuracy, not "cross-talk".


>The OSR (over-sampling ratio) is defined to be the ratio of

  Okay, I admit I don't know what that means, and I hope I never have to.  This is
my first delta-sigma converter.  I have other members on my team who will be glad
to worry about the absolute accuracy.  (We only need an honest 12-bits anyway).


>Are you able to connect the grounded ADC channels to AVSS? This could be worth testing.

  The 4th channel has its inputs shorted together, AND connected to AVSS and DVSS.
(Again, the first three channels have a common connection, but it is not connected
to anything but Ax- on the three A/D channels.)


>Can you short the positive and negative terminals of one of the ADC channels together
>and see if that channel still sees the same crosstalk as before?

  Good idea!  Okay, I shorted each of the three active channels with a paper clip
and their readings ARE affected by the other channels.  HOWEVER, when I place a
relatively high impedance DVM on a channel, that channel's A/D result is definitely
wildly affected by the input on the other channels, BUT the DVM shows NO CHANGE in
the voltage on the channel input (thus exhonerating my crummy potentiometer setup?).


  Anyway, this MSP430i2041 does not have enough horsepower to do what I originally
intended, so I rearranged the code so that I have only ONE interrupt service
routine.  Now, I have a timer interrupt that starts a single A/D conversion (set) and
sets a flag telling my main program loop when to send out another data packet.  When
the main loop sees this flag, it waits for the A/D conversion(s) to complete and
then reads the channel values and transmits them in a serial data packet.  There is
NO IMPROVEMENT in my "cross-talk" problem.  Shown below is my pertinent code:

//Initialize the A/D converter
SD24CTL    = SD24REFS;                        //use Internal Voltage-Reference
SD24CCTL0 |= SD24SNGL | SD24GRP | SD24DF | SD24OSR_32;        //Channel #0 is grouped with the next channel, and 2s-complement
SD24CCTL1 |= SD24SNGL | SD24GRP | SD24DF | SD24OSR_32;        //Channel #1 is grouped with the next channel, and 2s-complement
SD24CCTL2 |= SD24SNGL |           SD24DF | SD24OSR_32;        //Channel #2 is the Master-Channel, and 2s-complement

__interrupt void TA1_ISR(void)
{
A2D_TOGGLE_PORT |= A2D_TOGGLE_BITP;                           //turn the A/D Toggle signal ON
SD24CCTL2 |= SD24SC;                        //start A/D conversions again
SendPktFlag = 1;                        //flag is time for another IR output packet
return;      //(do ISRs need a return instruction???)          //dismiss this interrupt
}

 for (;;)                                //forever, until program termination
    {
     if (SendPktFlag)                                          //if it is time to send another IR packet
       {
        SendPktFlag = 0;                        //clear the flag for next time
        while (!(SD24CCTL2 & SD24IFG)) {};                //wait for Master-Channel conversion completion
    A2D_TOGGLE_PORT &= ~A2D_TOGGLE_BITP;                       //turn the A/D Toggle signal OFF
    SACount16 = SD24MEM0;                        //fetch the 16-bit result from Channel #0
    TVCount16 = SD24MEM1;                        //fetch the 16-bit result from Channel #1
    BVCount16 = SD24MEM2;                        //fetch the 16-bit result from Channel #2
       }

Hey Mitch, I really appreciate your interest and help here!

-eNick

This worries me: "(Again, the first three channels have a common connection, but it is not connected to anything but Ax- on the three A/D channels.)"

Without a connection to Vss, you have no idea what the common mode voltage on these differential inputs is. There are limits to what the inputs will tolerate.

  There isn't any common mode voltage.  The analog input voltages are
completely isolated from the power supply and ground for the chip.
The analog input voltages are generated from two alkaline batteries
in series, with the connection between the batteries treated as
analog common and connected to the A- terminals.  Potentiometers
are connected across the series battery stack, so that the wiper-arms
of the potentiometers will dish out a voltage between -1.6v and
+1.6v.  Each analog input channel has a resister divider to cut
the input voltage in half to keep it in the range -0.8v to +0.8v.
This works just peachy keen in my test setup, except for the fact
that a change in input voltage to one A/D channel causes a large
change in the A/D conversion value for the adjacent channels WITHOUT
any change being measured at the input terminals of those adjacent
channels.
  I should note that, in the real world final product, the isolation
situation will be reversed.  The analog inputs will be connected to
some voltages that can be as much as 8000 volts above earth ground
but that have small DIFFERENTIAL voltages between the A+ and A-
pins, and the power supply to the chip will be isolated via a
wireless charging scheme with a huge air gap good for 30 kilovolts.
Note that we have had systems like this working fine for many years
now, but we need to switch A/D vendors due to product obsolescence
of our existing part.

Thanks much for your interest, David.

-eNick

There is always common mode voltage. But it does appear from your description that the test setup shouldn't exceed the limits.

The data sheet doesn't have much information on the input circuitry. Certainly not in the detail that you usually get with a SAR ADC. But it does say that the differential input impedance is 400K and there is 200K from each input to AVss.

Based on that I put together a simple Spice model to play with. I found that changing the potentiometer setting on one channel would change the differential voltage on the other.

My model may not accurately represent what you are doing (I have no idea what resistor values you are using) and the resistors standing in for the analog input pins are just a guess.

I think that it is the 200K from each input to AVss that is doing you in. When I isolate the supplies to my two inputs, the interaction vanishes.

>I think that it is the 200K from each input to AVss that is doing you in.

  I agree. You have convinced me completely.  


>When I isolate the supplies to my two inputs, the interaction vanishes.

  We won't be able to do that in the real world product, but the interaction
also vanishes when I directly connect the A- pins to AVSS which I assume
will be fine when we go to a totally isolated power supply.  As I've
mentioned previously, people other than me are responsible for the actual
analog circuitry in the final product, so I am happy to say that I am done
with this.  I am ready to say that my problem is solved, but I will wait
one day to see if anyone else wants to weigh in.

  Thanks VERY MUCH, David, for taking the time to help me out here.

-eNick

It is sad that you have to convert those nice differential inputs into single ended inputs. At least the input voltage range goes below AVss.

You probably would have seen the problem a lot sooner if TI had included an equivalent circuit diagram for the SD24 analog inputs in the user guide like they do for their SAR ADCs.