Hello readers!
Something is going completely wrong. I thought I would have understand UCS but ... my Oscilloscope shows me something different than I have thought to be selected in the code .
Hardware:
I am using a MSP-TS430PN80USB. XT2 = 4MHz (as delivered), XT1 = 32768 Hz.
My uC is a MSP430F5529.
My aim:
- XT2 = 4MHz --> ACLK
- XT1 = 32kHz --> FLL --> DCOCLK --> MCLK (as high as possible)
- XT1 = 32kHz --> FFL --> DCOCLKDIV --> SMCLK = 216Hz (This frequency has to be!)
My problem:
My oscilloscope is connected to pin1.0 (ACLK) pin7.7 (MCLK) and pin2.2 (SMCLK)
Both pins are showing a frequency of about 180.505Hz.
But within my code (included a little bit further below) you will find the following line: " UCSCTL4 |= SELA_5 + SELM_3 + SELS_4;"
My questions:
- Does anybody can tell me why these pins (ACLK and MCLK) are showing a completely strange frequency?
- What further changes needs to be done to get closer to my aim?
- Please see question within subject, too. You will find more detailed description of this question a little bit further down.
My code is a mixture of the following sample codes from TI with some changes up to my task:
- MSP430F552x_UCS_07
- MSP430F552x_UCS_03
Many thanks in advance!!
Here is my code:
//------------------------------------------------------------------------------------------------
void Init_CLK(void)
{
//Pins:
P1SEL |= BIT0; // P1.0 from module (ACLK) - no LED
P1DIR |= BIT0; // P1.0 output
P2SEL |= BIT2; // P2.2 from module (SMCLK)
P2DIR |= BIT2; // P2.2 output
P7SEL |= BIT7; // P7.7 from module (MCLK)
P7DIR |= BIT7; // P7.7 output
// External Clock Sources:
// LF XT1:
P5SEL |= BIT4+BIT5; // Port select XT1 (P5SEL.5 don't care)
// HF XT2
P5SEL |= BIT2+BIT3; // Port select XT2 (P5SEL.3 don't care)
UCSCTL6 &= ~XT2OFF; // Set XT2 On
UCSCTL6 |= XCAP_2; // Internal load cap (8.5pF). I am using no external capacitors at the moment.
// (Supposed configuration for used Quartz: 8.7pF)
// Startup of quartz as XT1:
// XT1 is by default on as it is used default reference for the FLL - internal load caps?
// Loop until XT1,XT2 & DCO stabilizes
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);
// Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
}while (SFRIFG1&OFIFG); // Test oscillator fault flag
UCSCTL6 &= ~XT2DRIVE0; // Decrease XT2 Drive according to
// expected frequency
UCSCTL4 |= SELA_5 + SELM_3 + SELS_4; // Select sources SACLK=XT2 and MCLK=DCO
// SMCLK source = default = DCOCLKDIV
UCSCTL5 |= DIVA_0 + DIVS_5 + DIVM_0; // SMCLK = DCOCLKDIV / 32
// FLL
UCSCTL3 |= SELREF_0; // Set DCO FLL reference = XT1 (default)
__bis_SR_register(SCG0); // Disable the FLL control loop
UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx
UCSCTL1 = DCORSEL_5; // Select DCO range 24MHz operation
UCSCTL2 = FLLD_4; // Set DCO Multiplier for 16,777,216Hz
// D*(N + 1) * FLLRef = Fdco
// 16*(31 + 1) * 32768 = 16,7MHz
// Settings: N = n = defaults, D = 1
// (Defaults: n=1, D=2, N=31)
__bic_SR_register(SCG0); // Enable the FLL control loop
// Worst-case settling time for the DCO when the DCO range bits have been
// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
// UG for optimization.
// 32 x 32 x 12 MHz / 32,768 Hz = 375000 = MCLK cycles for DCO to settle
__delay_cycles(375000);
}
