Code examples of UART in USCI and USART

Hi Armen,

you can find code examples for this device here http://www.ti.com/litv/zip/slac118d.

Rgds
aBUGSworstnightmare

The main differenc ebetween the two is the interrupt handling and organization.

USART has separate interrupt vectors and edge-triggered  interrupt events, and the IFG adn IE flags are placed on global SFRs, while the USCI has joined vectors, an interrupt vector register and its own registers for all IE and IFG flags. Also, the USCI interrupts are level-triggered. As long as the IFG bit is set (and it won't clear automatically on ISR entry), the interrupt is still pending. You have to manually clear it or implicitely by reading the IV register or e.g. reading the RXBUF/writing to TXBUF.

Another (minor) difference is the oprional oversampling mode: if the source clock is much higher than the baudrate, it can be activated (acts as additional /16) and improves the bit level detection.

There are, however, two versions of the USCI. The older USCI, found in 2x devices, shares RX (and TX respectively) interrupt of A and B module in one ISR while the newer one shares RX an TX of A module and has a separate interrupt for the RX and BX of B module. Also, teh older USCI still uses global IE/IFG register while the newer one has its own IE and IFG register for each submodule (A or B).

Your code seems to be for an older USCI (from the name of UCA... but the usage of IE2)