Hi Champs,
a customer reported an issue with the GPIO interrupts. The same issue was already reported by Leo Hendrawan in 2014 and it might be linked to the specific configuration why this has not been seen more often:
Port1 pins 4, 5, 6 are configured as Inputs. P1DIR &= ~(BIT4 | BIT5 | BIT6);
Pin 4&5 are set to rising slope interrupt. P1IES &= ~(BIT4 | BIT5);
Pin 4&5 have activated GPIO interrupts. P1IE |= BIT4 | BIT5;
No it can be observed that a rising slope on pin 6 is also triggering an interrupt.
If interrupts for pin 4&5 are deactivated the issue with pin 6 is also gone.
if now the interrupt is activated for pin 4 there will as well be interrupts reported on pin 5 and 6.
same for pin 5. if the interrupt is activated on pin 5 you will also see interrupts for pin 4 and 6.
Maybe there is an easy solution to this. It would be great if you can look into this.
