Part Number: MSP430FR2676
I have configured our MSP430 as a SPI slave. As a test, upon receiving data, I'd like for the slave to invert the bits and send the byte back.
I see the master transmission on the logic analyzer but no response from the slave. We are not receiving SPI interrupts (although interrupts are enabled and other interrupts are working). All of this seems very straightforward so I'm wondering what I may have missed.
I have used the example project eusci_a_spi_ex1_slave as a guide for doing this, only changing to use SCI A1 (and my port configuration is performed in the BSP according to the method already in place in the CapTIvate examples).
Below is my BSP configuration for SPI port A1:
// PORT2 // P2.0: XOUT // P2.1: XIN // P2.2: INPUT. // P2.3: INPUT. // P2.4: SCK. // P2.5: MISO. // P2.6: MOSI. // P2.7: INPUT. P2OUT = (0); P2DIR = (0); P2SEL0 = (GPIO_PIN0 | GPIO_PIN1 | GPIO_PIN4 | GPIO_PIN5 | GPIO_PIN6); // Set primary function for pins 0,1,4,5,6. P2SEL1 = (0); // // Clear port lock // PM5CTL0 &= ~LOCKLPM5;
Below is the code to initialize SPI and the ISR.
void uC_SPI_Init(void)
{
//Stop watchdog timer
WDT_A_hold(WDT_A_BASE);
//Initialize slave to MSB first, inactive high clock polarity and 3 wire SPI
EUSCI_A_SPI_initSlaveParam param = {0};
param.msbFirst = EUSCI_A_SPI_MSB_FIRST;
param.clockPhase = EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT;
param.clockPolarity = EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW;
param.spiMode = EUSCI_A_SPI_3PIN;
EUSCI_A_SPI_initSlave(EUSCI_A1_BASE, ¶m);
//Enable SPI Module
EUSCI_A_SPI_enable(EUSCI_A1_BASE);
EUSCI_A_SPI_clearInterrupt(EUSCI_A1_BASE,
EUSCI_A_SPI_RECEIVE_INTERRUPT
);
//Enable Receive interrupt
EUSCI_A_SPI_enableInterrupt(EUSCI_A1_BASE,
EUSCI_A_SPI_RECEIVE_INTERRUPT
);
}
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=USCI_A1_VECTOR
__interrupt
#elif defined(__GNUC__)
__attribute__((interrupt(USCI_A1_VECTOR)))
#endif
void USCI_A1_ISR (void)
{
switch(__even_in_range(UCA1IV, USCI_SPI_UCTXIFG))
{
case USCI_SPI_UCRXIFG: // UCRXIFG
while (!EUSCI_A_SPI_getInterruptStatus(EUSCI_A1_BASE,
EUSCI_A_SPI_TRANSMIT_INTERRUPT
));
//Transmit data to master
EUSCI_A_SPI_transmitData(EUSCI_A1_BASE,
transmitData
);
//Receive data from master
receiveData = EUSCI_A_SPI_receiveData(EUSCI_A1_BASE);
// For testing purposes, just send back the bitwise inverse of what we received.
transmitData = (~receiveData);
break;
default:
break;
}
}
Thank you.
