CCS/MSP430FR6043: Sample Code

Hi Sumit,

http://www.ti.com/tool/MSP-ULTRASONIC-DESIGN-CENTER

Ling

Hi Ling,

There is no sample code about USS. can you share me the codes

Hi Sumit,

Ling

Hi Ling, 

Can you share me stand alone code for USS module?

Hi Sumit,

We don't have stand alone code. We recommend customer to use USS Design Center to develop the application.

Thanks,

Ling

i have one code, can you tell me the what is result variable in this program and how the code debug

#include <msp430.h>

#define OSCTYPE__CRYSTAL OSCTYPE_1

void HSPLL_init(void);
void SAPH_init(void);
void SDHS_init(void);

unsigned int flush_address[10],flush_data[1024],i;

#if defined(__TI_COMPILER_VERSION__)
#pragma DATA_SECTION(results, ".leaRAM")
#pragma RETAIN(results)
unsigned int results[1024] = {0};
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma location=0x5000
__no_init unsigned int results[1024];
#pragma required = results
#else
#error Compiler not supported!
#endif

int main(void)
{
WDTCTL = WDTPW | WDTHOLD; // Stop WDT

// Configure P1.0 as output for LED
P1OUT &= ~BIT0;
P1DIR |= BIT0;

// Disable the GPIO power-on default high-impedance mode to activate
// previously configured port settings
PM5CTL0 &= ~LOCKLPM5;

// Configure one FRAM waitstate as required by the device datasheet for MCLK
// operation beyond 8MHz _before_ configuring the clock system.
FRCTL0 = FRCTLPW | NWAITS_1;

// Clock System Setup
CSCTL0_H = CSKEY_H; // Unlock CS registers
// Per Device Errata set divider to 4 before changing frequency to
// prevent out of spec operation from overshoot transient
CSCTL3 = DIVA__4 | DIVS__4 | DIVM__4; // Set all corresponding clk sources to divide by 4 for errata
CSCTL1 = DCOFSEL_4 | DCORSEL; // Set DCO to 16MHz
// Delay by ~10us to let DCO settle. 60 cycles = 20 cycles buffer + (10us / (1/4MHz))
// __delay_cycles(60);
CSCTL3 = DIVA__1 | DIVS__1 | DIVM__1; // Set all dividers to 1 for 16MHz operation
CSCTL3 = DIVA__1 | DIVS__1 | DIVM__1; // MCLK = SMCLK = 16MHz
CSCTL0_H = 0; // Lock CS registers

SAPH_init();
SDHS_init();
HSPLL_init();

// Configure TA2.1 for 1/sec to trigger the pulse generation and toggle LED
TA2CCR0 = 9400;
TA2CCR1 = 4700;
TA2CCTL1 = OUTMOD_7 | CCIE; // Enable output signal to trigger PPG, enable Interrupt
TA2CTL = TASSEL__ACLK | TACLR | MC__UP; // Timer sourced from ACLK (VLO), clear timer

while(1)
{
__bis_SR_register(LPM0_bits | GIE); // Enter LPM3 w/interrupt
__no_operation(); // For debug
}
}

void HSPLL_init(void)
{
// Configure USSXT Oscillator
HSPLLUSSXTLCTL = OSCTYPE__CRYSTAL | USSXTEN;

// Set up timer to wait in LPM for crystal stabilization time = 4096 clocks for crystal resonator.
// For 8MHz XTAL, 4096 clocks = 512us. Using VLO = 9.4kHz, wait 5 timer clock cycles = 532us.
TA4CCR0 = 5;
TA4CCTL0 = CCIE; // Enable Interrupt
TA4CTL = TASSEL__ACLK | TACLR | MC__UP; // Timer sourced from ACLK (VLO), clear timer
__bis_SR_register( GIE); // Enter LPM3 w/interrupt
__no_operation(); // For debug

// Check if oscillator is stable
while((HSPLLUSSXTLCTL & OSCSTATE) == 0);

// Output oscillator on pin
HSPLLUSSXTLCTL &= ~XTOUTOFF;

// Init PLL
// Use the PLLM setting to get 80MHz output from our 8MHz input
// Equation: PLL output clock frequency x 2 = input clock frequency x (PLLM+1)
// Input clock frequency = 8MHz
// Desired PLL output clock frequency = 80MHz
// PLLM = 19
HSPLLCTL = PLLM4 | PLLM1 | PLLM0 | PLLINFREQ; //PLLM = 19, PLL input frequency > 6MHz

// Power up the UUPS to start the PLL
UUPSCTL |= USSPWRUP;

// Wait for UUPS to power up
while((UUPSCTL & UPSTATE_3) != UPSTATE_3);

// Wait for PLL to lock
while(!(HSPLLCTL & PLL_LOCK));
}

void SAPH_init(void)
{
// Set up the PPG settings
SAPHKEY = KEY; // Unlock the SAPH registers
SAPHPGC = PLEV_0 | PPOL_0 | 0x000A; // 10 excitation pulses, 0 stop pulses, output low when inactive, high polarity
SAPHPGLPER = 40; // Low phase = 4 HSPLL cycles = 50ns
SAPHPGHPER = 40; // High phase = 4 HSPLL cycles = 50ns
SAPHPGCTL = TRSEL_2 | PPGCHSEL_0 | PGSEL_0; // TA2.1 trigger, CH0 output, register mode
// SAPHPGCTL = TRSEL_2 | PPGCHSEL_1 | PGSEL_0; // TA2.1 trigger, CH1 output, register mode

// Set up the PHY to output PPG on dedicated CH0_OUT pin
SAPHOSEL = PCH0SEL__PPGSE; // Output PPG to ch0
// SAPHOSEL = PCH1SEL__PPGSE; // Output PPG to CH1

// SAPHICTL0 &= ~MUXCTL; // MUXCTL = 0
// SAPHICTL0 &= ~MUXSEL_0; // select CH0 as input

SAPHICTL0 &= ~MUXCTL; // MUXCTL = 0
SAPHICTL0 |= MUXSEL_1; // select CH1 as input

SAPHBCTL &= ~ASQBSC;
SAPHBCTL &= PGABSW; //Rx bias switch is closed (enabled).
SAPHBCTL &= CH1EBSW;
SAPHBCTL |= CPDA;

// Enable the PPG
SAPHPGCTL |= PPGEN;
}

void SDHS_init(void)
{
//Setup the SDHS with register mode
SDHSCTL0 = TRGSRC_0 | AUTOSSDIS_1 | DALGN_1 | DFMSEL_1; // Software trigger, automatic sample start after settling delay
SDHSDTCDA = 0x0008;
SDHSCTL1 = OSR_1; // OSR = 10 (80MHz/10 = 8MSPS). CS must set MCLK >= 8MHz.
SDHSCTL2 = 256; // SMPSZ = 256 samples
SDHSCTL6 = 0x1A; // PGA Gain 0.1 dB
SDHSCTL7 = 0xC; // MODOPTI = 0xC (80MHz PLL output frequency)
SDHSDTCDA = 0; // DTC transfer data to start of LEA RAM
SDHSIMSC = ACQDONE; // Enable acquisition done interrupt (after 256 samples transferred)
SDHSCTL3 = TRIGEN_1; // Enable trigger
SDHSCTL4 = SDHSON; // Turn on SD and start conversion
__delay_cycles(320); // Delay for PGA worst case 40us settling time
}

// Timer A2 interrupt service routine
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector = TIMER2_A1_VECTOR
__interrupt void Timer2_A1_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(TIMER2_A1_VECTOR))) Timer2_A1_ISR (void)
#else
#error Compiler not supported!
#endif
{
switch(__even_in_range(TA2IV, TAIV__TAIFG))
{
case TAIV__NONE: break; // No interrupt
case TAIV__TACCR1:
SDHSCTL5 &= ~SSTART;
SDHSCTL5 |= SSTART; // Start conversion
break;
case TAIV__TAIFG: break; // overflow
default: break;
}
}

// SDHS interrupt service routine
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector = SDHS_VECTOR
__interrupt void SDHS_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(SDHS_VECTOR))) SDHS_ISR (void)
#else
#error Compiler not supported!
#endif
{
switch(__even_in_range(SDHSIIDX, IIDX_6))
{
case IIDX_0: break; // No interrupt
case IIDX_1: break; // OVF interrupt
case IIDX_2: // ACQDONE interrupt
P1OUT ^= BIT0; // Toggle LED to show new cycle
__delay_cycles(10000);
__no_operation(); //put breakpoint here to view results
break;
case IIDX_3: break; // SSTRG interrupt
case IIDX_4: break; // DTRDY interrupt
case IIDX_5: break; // WINHI interrupt
case IIDX_6: break; // WINLO interrupt
default: break;
}
}

// Timer A4 interrupt service routine
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector = TIMER4_A0_VECTOR
__interrupt void Timer4_A0_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(TIMER4_A0_VECTOR))) Timer4_A0_ISR (void)
#else
#error Compiler not supported!
#endif
{
// Stop the timer and wake from LPM
TA4CTL = MC__STOP;
__bic_SR_register_on_exit(LPM3_bits | GIE);
__no_operation();
}

Hi Sumit,

We recommend customer to use USS Design Center to develop the application.

And you can refer to TI EVM example project source code for further study.

Technical documet from http://www.ti.com/product/MSP430FR6043/technicaldocuments

Ling

hello ling,

can you explain me the this code lines

#if defined(__TI_COMPILER_VERSION__)
#pragma DATA_SECTION(results, ".leaRAM")
#pragma RETAIN(results)
unsigned int results[1024] = {0};
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma location=0x5000
__no_init unsigned int results[1024];
#pragma required = results
#else
#error Compiler not supported!
#endif