MSP430F5438A: Clock Start-up Clarification

Part Number: MSP430F5438A

Hi Team,

As a follow on to  RE: MSP430F5438A: 1% of boards built will have the application code stall :

Previously the code started up the clock twice - once in bootstrap loader and once in main code. The clock startup in bootstrap loader has been removed, now relying on the default condition of 1MHz operation to run the processor.

The example code does not indicate that you need to wait for anything to stabilize before execution, is that correct?

The code is not running the FLL or internal oscillators, is the below setup correct and in the proper order for best operation?

After running at 1MHz to checksum the memory it jumps to the main application  where it sets power and clocking below :

WDTCTL = WDTPW + WDTHOLD;                   // Stop watchdog timer

 

__disable_interrupt();                 // Disable global interrupts

     

     /* ------   move up to full power --------      */

    SetVCoreUp (0x01);

    SetVCoreUp (0x02);

    SetVCoreUp (0x03);

 

            /*   ---  Set up XT2 for 12 mhz   -----      */ 

         P5SEL   |=  BIT2+BIT3;                     // Port select XT2

         UCSCTL6 &= ~XT2OFF;                       //  Enable XT2 

         

                                                   // set drive strength [01] for 12mhz

         UCSCTL6 &= ~(XT2DRIVE1);                 //  turn off drive bit 1

         UCSCTL6 |=   XT2DRIVE0 ;                //   turn on  drive bit 0

                     

          /*    ---------  Set up XT1  for 32khz    --------*/

         P5SEL   |=  BIT4+BIT5;                  // Select XT1

         UCSCTL6 &= ~(XT1OFF);                  //  XT1 On

        

                                                   // set drive strength [00] for 32khz

         UCSCTL6 &= ~(XT1DRIVE1);                 //  turn off drive bit 1

         UCSCTL6 &= ~(XT1DRIVE0);                //   turn off drive bit 1  

              

       /*    ------ Loop until XT1,XT2 & DCO stabilizes -------   */ 

  {

    UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);

                                            // Clear XT2,XT1,DCO fault flags

    SFRIFG1 &= ~OFIFG;                      // Clear fault flags

  }while (SFRIFG1&OFIFG);                   // Test oscillator fault flag  

       /*   -----     Set clock sources -------         */ 

        UCSCTL4 = 0X0055;  //Aclk= Xt1, SMclk = Xt2,  Mclk = XT2clk    

        UCSCTL1 |=  DISMOD  ;  // turn off modulation  

/*  ----      and  continue on ---------  */  

Thanks and let me know!!
Reed