Use of the FLL in the Unified Clock System

Roy Nordstrom said:

is the FLL capable of producing a DCOCLK in the vicinity of 20MHz

See the device datasheet for teh guaranteed minimum and maximum (not the absolute minimum/maximum) of the DCO frequencies for each RSEL setting and pick one.

Then program the factor between DCO and reference clock. The FLL will try to adjust the DCO so its average (!) frequency will be F_REF*FLLN. This means for REFO=32768, FLLN must be 610 (if FLLD==0, for default FLLD==1 it would be 305) for a DCO of 20MHz. But remember, it is only an average of 20MHz. The DCO will be constantly switched between the two step above and below 20MHz, resulting in clock jitter and temporary frequencies above 20MHz.

If your MSPs PCU core won't run on 20MHz, you can use the FLLD=1 and FLLN=305 setting. Then leave the MCLK on DCOCLKDIV. This way, MCLK will be ~10MHz.

You can even drive the DCO to 40MHz and use FLLD=1 and FLLN=610. If you then use DCOCLKDIV for (A/S)MCLK, you'll reduce the jitter a bit and also the frequency overshooting.

Roy Nordstrom said:

Is there a mathematical relationship  between the FLLREFCLK frequency, FLL settings and the DCOCLK output frequency

AVG[DCOCLK] = F_REF*2^FLLD*FLLN.

Anyway, the DCO has only 32 taps and there are only 8 RSEL settings, so the DCO can only have one of 256 different output frequencies (and there may be some doubles too, as the RSEL regions overlap). Any frequency between these 256 discrete ones is done by modulating between one DCO setting and the next higher. The modulation has a granularity of 1/32. The FLL will try to adjust DCO tap selection and modulation to the value that fits the desired frequency, yet the outcome is just a mixture of two (or more) frequencies building an average over some reference clock cycles.