MSP430FR2355: Is it possible to detect phase shifts in a 416Khz pulse using the msp430FR2355?

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//******************************************************************************
//  MSP430FR235x Demo - ADC, Sample A1, internal 1.5V Ref, Set P1.0 if A1 > 0.5V
//
//  Description: This example works on Single-Channel Single-Conversion Mode.
//  Software sets ADCSC to start sample and conversion - ADCSC automatically
//  cleared at EOC. ADC internal oscillator times sample (16x) and conversion.
//  In Mainloop MSP430 waits in LPM0 to save power until ADC conversion complete,
//  ADC_ISR will force exit from LPM0 in Mainloop on reti.
//  If A1 > 0.5V, P1.0 set, else reset.
//  ACLK = default REFO ~32768Hz, MCLK = SMCLK = default DCODIV ~1MHz.
//
//               MSP430FR2355
//            -----------------
//        /|\|                 |
//         | |                 |
//         --|RST              |
//           |                 |
//       >---|P1.1/A1      P1.2|--> LED
//
//
//   Cash Hao
//   Texas Instruments Inc.
//   November 2016
//   Built with IAR Embedded Workbench v6.50.0 & Code Composer Studio v6.2.0
//******************************************************************************
#include <msp430.h>
unsigned int ADC_Result;

int main(void)
{
    WDTCTL = WDTPW | WDTHOLD;                                 // Stop WDT

    // Configure GPIO
    P6DIR |= BIT6;                                            // Set P6.6 LED to output direction
    P6OUT &= ~BIT6;                                           // P6.6 LED off

    // Configure ADC A0 pin
    P1SEL0 |= BIT0;
    P1SEL1 |= BIT0;

    // Disable the GPIO power-on default high-impedance mode to activate
    // previously configured port settings
    PM5CTL0 &= ~LOCKLPM5;

    // Configure ADC10
    ADCCTL0 |= ADCSHT_2 | ADCON;                              // ADCON, S&H=16 ADC clks
    ADCCTL1 |= ADCSHP;                                        // ADCCLK = MODOSC; sampling timer
    ADCCTL2 &= ~ADCRES;                                       // clear ADCRES in ADCCTL
    ADCCTL2 |= ADCRES_2;                                      // 12-bit conversion results
    ADCIE |= ADCIE0;                                          // Enable ADC conv complete interrupt
    ADCMCTL0 |= ADCINCH_1 | ADCSREF_1;                        // A1 ADC input select; Vref=1.5V

    // Configure reference module
    PMMCTL0_H = PMMPW_H;                                      // Unlock the PMM registers
    PMMCTL2 = INTREFEN | REFVSEL_0;                           // Enable internal 1.5V reference
    while(!(PMMCTL2 & REFGENRDY));                            // Poll till internal reference settles

    while(1)
    {
        ADCCTL0 |= ADCENC | ADCSC;                            // Sampling and conversion start
        __bis_SR_register(LPM0_bits | GIE);                   // LPM0, ADC_ISR will force exit
        if (ADC_Result > 0x555)                               // 0x555 represent 0.5V
            P6OUT &= ~BIT6;                                   // Clear P6.6 LED off
        else
            P6OUT |= BIT6;                                    // Set P6.6 LED on
        __delay_cycles(5000);
    }
}

// ADC interrupt service routine
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=ADC_VECTOR
__interrupt void ADC_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(ADC_VECTOR))) ADC_ISR (void)
#else
#error Compiler not supported!
#endif
{
    switch(__even_in_range(ADCIV,ADCIV_ADCIFG))
    {
        case ADCIV_NONE:
            break;
        case ADCIV_ADCOVIFG:
            break;
        case ADCIV_ADCTOVIFG:
            break;
        case ADCIV_ADCHIIFG:
            break;
        case ADCIV_ADCLOIFG:
            break;
        case ADCIV_ADCINIFG:
            break;
        case ADCIV_ADCIFG:
            ADC_Result = ADCMEM0;
            __bic_SR_register_on_exit(LPM0_bits);              // Clear CPUOFF bit from LPM0
            break;
        default:
            break;
    }
}