MSP432P401R: MSP432P401 older MSP432WARE 3.4 example issues

kwa

Part Number: MSP432P401R

After some study of MSP432Ware 3.4_xx and experiments with timer_A0 interrupts that don't activate themselfs there must be reason

Example used below is not driverlib, it's a pure register level example using one timer and one interrupt.

// - - - - -

//   Texas Instruments Inc.
//   June 2016 (updated) | November 2013 (created)
//   Built with CCSv6.1, IAR, Keil, GCC
//******************************************************************************
#include "msp.h"

int main(void) {
    WDT_A->CTL = WDT_A_CTL_PW |             // Stop WDT
            WDT_A_CTL_HOLD;

    // Configure GPIO
    P1->DIR |= BIT0;
    P1->OUT |= BIT0;

    TIMER_A0->CCTL[0] = TIMER_A_CCTLN_CCIE; // TACCR0 interrupt enabled
    TIMER_A0->CCR[0] = 50000;
    TIMER_A0->CTL = TIMER_A_CTL_SSEL__SMCLK | // SMCLK, continuous mode
            TIMER_A_CTL_MC__CONTINUOUS;

    SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk;    // Enable sleep on exit from ISR

    __enable_interrupt();
    NVIC->ISER[0] = 1 << ((TA0_0_IRQn) & 31);

    while (1)    {
        __sleep();
        __no_operation();                   // For debugger
    }
}

// Timer A0 interrupt service routine
void TA0_0_IRQHandler(void) {
    TIMER_A0->CCTL[0] &= ~TIMER_A_CCTLN_CCIFG;
    P1->OUT ^= BIT0;
    TIMER_A0->CCR[0] += 50000;              // Add Offset to TACCR0
}

This example A looks complete but really at CCS 6.1.3 these interrupts don't exist.

Now as the Cortex uses much presets, dependencies and modes, like the activating interrupts before they can be used,

does this mean each time or should this preset expected to be static as a default until it's released ?

Some other examples B use interrupts another way, they are really activated each time before they are used ?

while(1)     {
        MAP_GPIO_clearInterruptFlag(GPIO_PORT_P1, GPIO_PIN1 | GPIO_PIN4);
        MAP_UART_enableInterrupt(EUSCI_A0_BASE, EUSCI_A_UART_RECEIVE_INTERRUPT);
        MAP_Interrupt_enableInterrupt(INT_EUSCIA0);
        MAP_Interrupt_enableInterrupt(INT_PORT1);
        MAP_Interrupt_enableInterrupt(INT_TA1_0);
        MAP_Interrupt_enableInterrupt(INT_TA2_0);
        MAP_Interrupt_enableMaster();
        MAP_PCM_gotoLPM0();
    }

Now this another MSP432Ware 3.4_xx example B activates interupts as expected, but these two example principles A and B are now different so

the final question is are the MSP432WARE 3.40_xx Register level examples working or not ? Or is there some other

unknown reason behind this issue, tools,versions, libraries etc.

Actually MSP432 documentation doesn't very detailed describe above definition life-times if they really have run-time lifetime.

over 4 years ago

0 PM over 4 years ago

TI__Mastermind 27145 points

Hi,

We will look into it and get back to you ASAP. Please bear with us.

Thanks,

0 kwa over 4 years ago in reply to PM

Prodigy 100 points

Ok, actually one possibly missing thing in the example A was the counter device TA0 interrupt activation, TAIE is not set ?

At least this prevent it creating interrupts, but adding this didn't still activate the interrupt service function...?

Hmmm...

0 kwa over 4 years ago in reply to kwa

Prodigy 100 points

I think the solution is found between MSP432 driver_lib and register level MSP432WARE c-file examples, the interrupts were not in use at all, which can lead to misundertandings when empty CCS project is waiting.

Driver_lib does more things behind the stage than the pure Register level c-file examples, which leaves need to manually include the interrupt service functions to system use, by introducing the user interrupt functions as a extern files to system start up file, startup_msp432p401_ccc.c when CCS compiler is used.

The 'default_ISR' is substituted by the device interrupt function name in the table in this file, following the comments column right, maintaining the interrupt order in startup_msp432p401_ccc.c.

So MSP432WARE 3.40_00 has set of register level C-file examples and they are useful and compact, but the starting step to use of them is not very obvious in general or is documented very lightly elsewhere.

Hopefully this helps someone else activating the missing interrupts

0 Bruce McKenney47378 over 4 years ago in reply to kwa

Guru 91600 points

Yes, earlier versions of the supplied startup.c file populated the vector table with "defaultISR" (or some such), and to add an ISR one had to hand-modify the startup.c as well. Later versions populate the table with the appropriate (CMSIS-form) names as "weak externals" that resolve to Default_Handler if absent.

And those older startup.c files are still floating around in the older examples (I still have a copy of 3.30.00.01 since I'm a packrat), so it's something to watch out for. I'm not sure that DriverLib (per se) affects this, though.

The "weak externals" method is I would say the better one.

[In case it's not obvious: I'm agreeing with you.]

0 kwa over 4 years ago in reply to Bruce McKenney47378

Prodigy 100 points

Ok, thanks for comments, and really newer MSP432WARE and at CCS 7.4 internal presets are changed, these are no more

manually maintained.

But now to next experiments as the goal is to get quite precise timing pulse to output IO pin with a minimal sw interaction from

this TA counter.

I believe interupts add some delays, it's ok if it's constant, but direct internal signal would be better thought the counters have high priorities.

After some study of timer 16bit timer, noticed the OUTMODE signalling difficult, as the mode, 3 set-reset didn't

shown at the P7.3 TA0.0 pin of MSP432P401R, actually they didn't shown at any mode correctly.

Now, some clarification is needed this OUT signal use cases, the OUTMODE_0 (1..7) is mentioned, but

1) should this be preset at CCR register initalization ?

2) or it is set to CCR register at interrupt function at the time of compare match ?

3) this probably is hw-logic interface to ports/other inputs, so probably it does need preset in other modes than OUTMOD 0, so

should this be set to CCR register at interrupt function by setting this needed OUT value 0 or 1 to CCRx register use ?

Timer_A document at page 606 shows this counter schematic, and OUT bit input has AND gate to OUT6 signal (CCR6 reg example) but

I think this logic is connected to TimerAx(1..4) and the second device outputs, so if the pin P7.3 is reserved to TA0.0

then any TA0 CCRx register compare output can control the P7.3 pin ?

This compare mode should be independent of capture inputs CCIS,SCS as the interrupts activate by CCRn and CCR0, but the OUTMODE

signals don't, or if there is timing or phase difference between comparator output and clock signal at D-FF.

A long story, so shortly is there a MSP432P401 example of OUTMODE mode 0 use, eg. using CCR1-> CCR0 or using CCR3->CCR0 for multiple compares during counting please ?

Regards

0 Bruce McKenney47378 over 4 years ago in reply to kwa

Guru 91600 points

If I understand your question correctly, you're just looking for a pulse train. The keyword here is "PWM". Most people use the term "PWM" to imply varying the pulse width, but if you never vary the pulse width it's just a (fixed) pulse train. You can set up a pulse train once and never touch it, and the hardware will generate it for you (in particular: no ISRs are needed).

The OUTMOD describes what the waveform looks like and the CCR(s) define the frequency and pulse width. CCR0 is part of (almost) every OUTMOD, so you should plan on using TA0.1 and up, not TA0.0.

Example msp432p401x_ta1_16 generates two pulse trains, i.e. fixed PWM streams, with designated pulse widths (common frequency since it's the same timer):

http://dev.ti.com/tirex/explore/node?node=AM9ftBfVYSFvblITRKXJwQ__z-lQYNj__LATEST

[Edit: Slightly better link]

0 kwa over 4 years ago in reply to Bruce McKenney47378

Prodigy 100 points

Hi and thanks for the reply and comments.

Yes the target is to get 100ms delay,activated by the sw and this timing output should be get to external IO pin. The confusion was the misunderstanding whether the multiple CCR compare results are combined to common IO pin or then later.. it became clear they each have their own private IO ports where they output the events.

No worries, complex logic can be sometimes such.

Thanks for the guidance

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MSP432P401R: MSP432P401 older MSP432WARE 3.4 example issues