Other Parts Discussed in Thread: MSP432E401Y
Hi,
I bought a kit that includes the two development boards in the title. I have no issues using the the ti SPI, it all works as expected. However I'm trying to optimize the transfer speeds because the SPI routine is a big time consumer in the function loop. The DAC has a protocol of 32 bit packets (asserting CS at the start and de-asserting it at the end of those 32 bits), meaning that I'm populating the transactions with 4 bytes with 8 bit SPI frames.
Now, I've tried using DMA with 4 bytes and the transfer itself is very fast and it sends the entire frame correctly and using hardware CS (SS) it asserts that pin at the appropriate time with little latency between CS and the start and end of the packet. Unfortunately setting up the DMA transfer imposes some latency before the transaction starts.
Conversely, trying it with polling has much lower latency before the start of the transaction, but it forces me to use software CS, in order to keep CS asserted during the entire 32 bit packet. I've noticed that using software CS also imposes a lot of dead time before the transaction starts.
So after this set up, I'm asking if it is possible to use hardware CS with a polling transfer, or populate the FIFO with the data and have CS toggle itself at the right time, instead of after every frame?
