• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 79 subscribers
  • Views 511 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

MSP430 ADC10 Timing

Joel Pigdon
Prodigy 10 points

Other Parts Discussed in Thread: MSP430F4152

Hi all,

I'm working with the MSP430F4152, I would like to implement an FSK demodulation in a manner similar to app note slaa037.

I would like to use the inbuilt ADC10 to do the sampling at 6800Hz.

However I do not have any timers free to do the timing.

I would like to do the input sampling using a combination of FLL+ DCO adjustment and ADC10 delay.

First of all, is each conversion using the ADC10 exactly 13 + S/H time ADC10CLK cycles, when operating in repeat sequence of channels mode, including utilizing the Data Transfer Controller?

Also, do all ADC10 devices support all 16 ADC10 INCHx values just some have those inputs tied to (Vcc-Vss)/2.

Summing up, can someone confirm my calculations for obtaining a 6800Hz sample time using the ADC10 repeated sequence of channels mode

ACLK @ 32768Hz FLL divider of 4 and DCO multiplier of 59 gives CLK of 786432Hz which the F4152 can handle with supply > 3.0V

ADC10CLK divider = 5

gives ADC10CLK = 1572864Hz

Repeated sequence of channels mode for 11 channels x (S/H of 8 clock cycles + 13 cycles conversion time) = 231 ACD10CLK cycles per sample 

= sample rate of 6808.9Hz, which should be good enough

Does anyone see any major problems with this approach.

Thanks

Joel

 

  • 0
    Guru 227245 points

    Joel Pigdon said:
    First of all, is each conversion using the ADC10 exactly 13 + S/H time ADC10CLK cycles, when operating in repeat sequence of channels mode, including utilizing the Data Transfer Controller?


    Not exactly. There's the TSYNC time that adds to the TSH time and which (while in your setup, SHI and ADC10CLK are in sync) might be enlarged by some delay cause by the channel switching. I dimly remember reading something about this somewhere, but I'm not sure whether it applies to the ADC10 or ADC12 or SD16.

    To be sure, you should calculate the optimum settings and then check whether it is indeed your desired frequency or 1 or 2 cycles off. Then adjust the timing.

    Keep in mind that the larger you choose the S&H time, the stronger the low-pass effect youapply to the input. Even if the total time per conversion is constand, a higher clock and a longer S&H time will enlarge the S&H time (increasing the low-pass effect) and shorten the conversion time (and therefore the current draw ffrom the S&Hbuffer) resulting in better results.

**Attention** This is a public forum