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MSP430FR2433: Sampling rate

FRANK1
Expert 8725 points
Part Number: MSP430FR2433


Hi sir,

I was stuck with a problem with a microcontroller Its regarding the ADC on msp430fr2433.

The microcontroller datasheet mentions a 200ksps sampling rate.

But I would like to know the response of the ADC at higher sampling rates like around 0.8 to 1.2 maps If it faithfully produces all the higher frequencies.
Please can you help me with that.

Thank u.

  • 0
    Guru 100825 points

    I'm supposing "maps" was intended to be "Msps". Putting together data sheet (SLASE59D) Table 5-21 and user guide (SLAU445I) Sec 21.2.5, my calculator says the maximum theoretical sample rate (ADCCLK=16MHz) is about 0.94Msps, so 1.2Msps can't be achieved.

    Doing this would violate most of the specifications in Table 5-21. I'll let TI speak for itself, but my guess is that there is no "Specification for running outside the Specification". I suppose you could try it and see what happens.

    Of particular interest is the minimum sampling time, which is a matter of Time (capacitor charging) not Clocks, and supposes a Very low impedance source. The 2us minimum by itself limits you to about 0.35Msps. From experience, if you run with too short a sample/hold time you will not get linear results. Running the ADCCLK >5MHz will add to this.

  • 0
    TI__Genius 14775 points

    Mark,

    This is a great question! The answer simply has to do with the inherent limitations of the ADC core and what speeds it is specified to operate at.

    The first thing we need to keep in mind is how many clock cycles it takes to first sample the analog signal and then convert the result. According to the datasheet in Table 5-21, the worst case minimum time needed to sample the analog signal is 2us which equates to 11 ADCCLK cycles if we are running at the maximum specified ADCCLK frequency of 5.5MHz:

    According to the user's guide in Figure 21-3, the ADC conversion takes 12 ADCCLK cycles:

    When we add all of this up we end up with 11+12 = 23 ADCCLK cycles to complete 1 full sample & conversion. Running at full ADCCLK speed this puts us at 4.2us for a full sample & conversion which equates to approximately 239.13ksps which is realistically the fastest specified sampling rate this ADC can achieve when VCC is 3V. With this in mind, you are more than welcome to exert the ADC beyond its limitations and recommendations to test it's performance but we cannot guarantee that it will perform within the specification performance and linearity parameters given in Table 5-22 of the datasheet.

    I hope this helps answer your question and explains why we market it as approximately a 200ksps ADC.

    Best regards,

    Matt Calvo

  • 0 in reply to Matt Calvo
    TI__Expert 8725 points

    Thank u so much.

    It's very helpful.

    Have a good day.

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