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MSP430FR5994: Master SCL for checking ACK is missing or come to late

Hardy Zissel
Intellectual 510 points
Part Number: MSP430FR5994


I have to read a FLASH memory via I2C. The MSP430fr5994 is the master. It send start condition and the bus address. Now the clock (SCL) is stay constant low. The slave holds the SDA line low for transmitting the ACK bit. After a long time out the slave leave the SDA line to high and the master send one SCL bit (from low to high to low). The NACKIFG is 1. But if the master send the first address byte (timer controlled) shortly after the 8-th clock bit then the master is send 9 clock bits. But the slave taks the first of this 9 clock bits as the clock for checking ACK. The next 8 bits are the first address byte and the clock bit for checking the slave ACK is missing and so one. I think the problem is the first missing clock bit for checking the slave ACK after the bus address. What have I to initialise that the master send this bit bevore transmitting the first address byte?

Best Regards
Hardy

  • 0
    Guru 100935 points

    From your description, your program (Master) is taking too long to set TXBUF in response to the TXIFG, and thus stretching the clock for long enough to trigger your Slave to time out; once that has happened, and/or you've received a NACK, you should consider the transaction Failed. Unless this is a case of "busy polling", there's no reason to believe you'll succeed if you blindly retry.

    It would probably be useful to know the part number for your I2C Flash device, and maybe to see your code which handles the TXIFG.

    Also, what does "(timer controlled)" mean?

  • 0 in reply to Bruce McKenney
    Intellectual 510 points

    Thank you for the fast answer.

    The FLASH is a ST25DV from ST Microelectronics. It is a NFC chip.

    Sorry, it wars not good to write "timer controlled". I had have make a test with a time to separate 2 bytes for around 2 clock periodes to see if the clock for ACK comes at the end of one byte or at the begin of the next byte. So I saw that the clock for ACK is coming at the begin of the folloing byte. Do you can say if it must be so or is is a problem? My idea wars it is usual to check if the ACK wars comming before send the next byte.

  • 0 in reply to Hardy Zissel
    Guru 100935 points

    The ACK is considered to follow the byte it acknowledges. If a Master Transmitter is slow to fill TXBUF in response to the TXIFG, the I2C unit will hold SCL low (stretch the clock) until TXBUF is filled --- typically a few 10s of usec, but forever if need be. Once the ACK cycle is done, the next (Tx) byte will proceed immediately, which might create the illusion you see.

    I encourage you to study User Guide (SLAU367O) Fig 32-12, which gives the state diagram for the Master Transmitter, in particular the box (near the top) that says "Bus stalled", which I suspect is where your Slave timeout (25ms) is happening. Besides your code, you need to avoid breakpointing while in this state (since the Slave doesn't know about that).

  • 0 in reply to Bruce McKenney
    TI__Genius 17960 points

    Hello Hardy,

    in addition to Bruce's recommendation please also consider our main application report for debugging I2C and other serial communication with MSP430.

    Best regards

    Peter

  • 0 in reply to Peter Spevak
    Intellectual 510 points

    Thanks for your supply. Now I have implemented the reading prozess done.

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