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MSP430FR5994: MCU energy per clock cycle

Rosh Mendis
Intellectual 730 points
Part Number: MSP430FR5994
Other Parts Discussed in Thread: ENERGYTRACE

Hi

Is there are info or previously measured data on how much energy is consumed by the MSP430FR5994, per clock cycle (at 16MHz) in active mode ?

Is this specified somewhere in the datasheet ?

thanks

Rosh

  • 0
    TI__Genius 17960 points

    Hello Rosh,

    actually we're not specifying the charge required per instruction. What you can find in the device datasheet are the current consumption values for various scenarios in active mode. Please see table 5.4 Active Mode Supply Current Into VCC Excluding External Current.

    The reason for not specifying charge per instruction cycle is the complexity and number of different scenarios. Keep in mind, the main portion of the current related to CPU activities is mainly consisting of the charges required for the switching. But the charges are dependent on many factors, previous state of the CPU, address bus, memory location, execution from FRAM, RAM, Cache, processed data. So if you multiply all these options, you might guess, we would end up at thousands of values.

    On the other hand, if you take the values from the above mentioned table in the datasheet, you can estimate the average current per instruction. The other approach you could take is generate a test code sequence on your own, and perform a measurement for this specific case.

    Best regards

    Peter

  • 0 in reply to Peter Spevak
    Intellectual 730 points

    Would the energy cost vary depending on how much data is in the FRAM or how much FRAM space is used ?

    e.g., code containing a 1024 byte buffer stored and initialized in FRAM vs. 8192 buffer stored and initialized in FRAM, but at a specific moment in runtime the data buffer is unused.

    in the above scenario, would the latter case consume more energy, as more FRAM is utilized ?

  • 0 in reply to Rosh Mendis
    TI__Genius 17960 points

    Hi Rosh,

    this is difficult to predict. Please see our User's Guide documentation and the details of FRAM code execution and operation. In addition, there are some other useful documents. In this one there is even a specific chapter on power consumption

    Just one key word is the Cache, which is used to reduce the FRAM read access ratio. Dependent on the code, the location of the instructions, the Cache hit ratio and thus the current consumption can vary. This is not necessarily dependent on the code size or amount of data handled. For further information please check out the details in our documentation.

    Best regards

    Peter

  • 0 in reply to Peter Spevak
    TI__Genius 17960 points

    Hi Rosh,

    is there still something we can do for you on this topic? Please let us know. Many thanks in advance.

    Best regards

    Peter

  • 0 in reply to Peter Spevak
    Intellectual 730 points

    One last related question:

    I also noticed FRAM write energy (e.g., copying data from SRAM to FRAM) is generally a little higher than FRAM read energy (e.g., copying data from FRAM to SRAM). Is this correct ?

  • 0 in reply to Rosh Mendis
    TI__Genius 17960 points

    Hi Rosh,

    if you would perform just one transfer with one and the same data in the one and the opposite direction, the energy consumption should be the same.

    The difference you're experiencing though, is probably related to Cache operation. I assume you have been transferring reasonable amount of data. In such a case the transfer from FRAM to RAM will be happening based on a small code loop in FRAM, which probably fits into the 64Bit Cache, means the Cache fetches once the code loop, and all the following runs will be executed from Cache. The opposite direction will not work with Cache only, as you will be writing to FRAM somewhere else, compared to the location, where the code for the write instruction is located.

    Unfortunately from the user's side it is basically impossible to predict, when and how much of code execution will be happening from Cache or from direct FRAM accesses.

    Best regards

    Peter

  • 0 in reply to Peter Spevak
    Intellectual 730 points

    - I'm transferring data using the DMA (block transfers with sizes 1 to 256 words)

    Yes the cache could explain the read energy being lower.

    However, I also observed another phenomenon related to MCU energy consumption. Two consecutive runs of the same code (e.g., the DMA based FRAM read code) consumes different amounts of energy sometimes the variance could be up to 2-10% different run to run. I'm using EnergyTrace to measure the energy consumption. Nothing is changed in the code or CCS setting.

    Could this be something to do with the way the measurements are made in EnergyTrace or to do with power circuitry on the MSP430FR5994 launchpad ?

    thanks

  • 0 in reply to Rosh Mendis
    TI__Genius 17960 points

    Hi Rosh,

    as you see the complexity of these topics should not be underestimated.

    In respect of the EnergyTrace, if you intend to perform reasonable analysis, I would recommend you using a professional tool. The EnergyTrace has certain capabilities, which in respect of the cost of the implementation are certainly exciting, but for very detailed and professional measurements it is absolutely not sufficient. The main problem with it is the method of the current measurement. The tool is using a charge transfer method, charging and discharging a known capacitor. The energy consumption is then derived from the number of required recharge cycles of the capacitor, which is pendelling between the set charge discharge thresholds. While the integration over longer periods is quite accurate, it gives you in very detail often a misleading picture, as even with same level of current consumption due to the precondition running into your test sequence, the profile, means number and especially the timing of the recharge events might not be the same.

    The next thing to be kept in mind is the nature of the currents of an MCU or other digital clocked devices. We're looking here at devices, where the main portion of the currents consists of charging and discharging of capacitances, let it gate capacitances, let it line capacitances of buses, memory, and all the other components involved in respective activities. The required charge events are of course also dependent on the history. This means of course in most of the cases executing two equal instructions after another will give you for the two runs two different power profiles. And this is not considering the influence of Cache on top.

    But I am afraid we're reaching here a level of details, which leads to an academic level of these things. While probably interesting for you, it exceeds the level of the needs of our customer base. Thus if interested in more details, please check the content of the documents I pointed you to and in addition there is for sure some specific literature on these topics in university libraries.

    Best regards

    Peter

  • 0 in reply to Peter Spevak
    Intellectual 730 points

    Hi Peter,

    thank you, I appreciate your advice.

    Regarding energy trace -

    According to this page, the energy trace accuracy is around 2-5%, depending on the current and voltage

    https://processors.wiki.ti.com/index.php/EnergyTrace_for_MSP432

    But I also found on this document that when using energytrace, usb hubs and long cables should not be used to avoid voltage drops

    https://processors.wiki.ti.com/index.php/EnergyTrace_for_MSP432

    maybe all these factors (including what you have stated) combine to give the measurement variation I see.

    thanks

    Rosh

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