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MSP432P401R: What happens when two interrupts trigger at the same time?

Michael Wu1
Prodigy 30 points

Part Number: MSP432P401R

Hi, overall I'm quite inexperienced with microcontrollers, so please excuse me if this question is quite basic.

I'm creating a project in CCS using SysConfig to configure my MSP432. I currently have three interrupt enabled pins -- on a falling edge, it causes two different ADC's to sample, and some math is performed on the two measurements, and some data is sent out using UART.

One question that I have is what behavior occurs if two falling edges occur at the same time? Does one of the interrupts get completely ignored? Or does one of them get "buffered" and the callback functions execute sequentially? In SysConfig, it seems that the interrupt priority is global and affects the priority of all interrupts, so there doesn't seem to be a way to assign different priorities to  the different interrupts.

Regards,

Michael Wu

  • 0
    Guru 99105 points

    If two different IRQs of the same priority trigger at Exactly the same time (or are pending with interrupts are enabled), the lower-numbered IRQn goes first. The other stays pending until the ISR for the first completes. [Ref DDI0403E Rev B, Sec B1.5.4]

    Two pins in the same port share an IRQ. You need to check the IFG register (really IFG&IE) to see if more than one triggered.

    You can set IRQ priority using NVIC_SetPriority.

  • 0 in reply to Bruce McKenney
    Prodigy 30 points

    Hey Bruce,

    Thanks for the reply. What exactly do you mean by the same "port?" How can I check if my pins (P5.4, P5.5, P5.6) are in the same port?

    What happens if multiple interrupt requests trigger at the same time with the same IRQ number?

  • 0 in reply to Michael Wu1
    Guru 99105 points

    P5.4, P5.5 and P5.6 are all on port "P5". [Ref MSP432P TRM (SLAU356H) Sec 12.1]

    The NVIC only has a single pending bit per IRQn. If a source (device,e.g.) sets pending an IRQn which is already pending, it has no effect. Typically a device which has more than one interrupt cause, but has a single IRQn, has a separate register e.g. the Port IFG register with more detail.

  • 0 in reply to Bruce McKenney
    Prodigy 30 points

    Got it. So if I wanted to avoid checking the IFG register, would it suffice in my case to move the other interrupts to other pins in a different port, i.e. P1-4, P6-...?

  • 0 in reply to Michael Wu1
    Guru 99105 points

    Yes, you could. But checking a register is much cheaper than an (additional) ISR call.

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