MSP430F2618 UART Interrupt

I am trying to get one of the example codes from TI to work. It is related to using the UART interrupt, and having the ISR echo back a character through the UART RX interrupt line.

I wanted to test to see if the setup was correct, but when I run and debug it, it seems like the ISR is not firing. I modified the code by adding a transmit 0x41 character so the ISR will trigger, but when I put a breakpoint in the ISR, the program does not stop...

I have not really worked with MSP430 before and I am not too familiar with the syntax of checking the flags to see if the transmission can be performed or not

BTW, I am using both Code Composer Studios and IAR and it both doesn't work.

Can anyone help?!?!

//******************************************************************************

//   MSP430x26x Demo - USCI_A0, 115200 UART Echo ISR, DCO SMCLK

//

//   Description: Echo a received character, RX ISR used. Normal mode is LPM0.

//   USCI_A0 RX interrupt triggers TX Echo.

//   Baud rate divider with 1MHz = 1MHz/115200 = ~8.7

//   ACLK = n/a, MCLK = SMCLK = CALxxx_1MHZ = 1MHz

//

//             MSP430F261x/241x

//             -----------------

//         /|\|              XIN|-

//          | |                 |

//          --|RST          XOUT|-

//            |                 |

//            |     P3.4/UCA0TXD|------------>

//            |                 | 115200 - 8N1

//            |     P3.5/UCA0RXD|<------------

//

//   B. Nisarga

//   Texas Instruments Inc.

//   September 2007

//   Built with CCE Version: 3.2.0 and IAR Embedded Workbench Version: 3.42A

//******************************************************************************

#include  "msp430x26x.h"

void main(void)

{

  WDTCTL = WDTPW + WDTHOLD;                 // Stop WDT

  if (CALBC1_1MHZ ==0xFF || CALDCO_1MHZ == 0xFF)                                     

  {  

    while(1);                               // If calibration constants erased

                                            // do not load, trap CPU!!

  }    

  BCSCTL1 = CALBC1_1MHZ;                    // Set DCO

  DCOCTL = CALDCO_1MHZ; 

  P3SEL = 0x30;                             // P3.4,5 = USCI_A0 TXD/RXD

  UCA0CTL1 |= UCSSEL_2;                     // SMCLK

  UCA0BR0 = 8;                              // 1MHz 115200

  UCA0BR1 = 0;                              // 1MHz 115200

  UCA0MCTL = UCBRS2 + UCBRS0;               // Modulation UCBRSx = 5

  UCA0CTL1 &= ~UCSWRST;                     // **Initialize USCI state machine**

  IE2 |= UCA0RXIE;                          // Enable USCI_A0 RX interrupt

  __bis_SR_register(LPM0_bits + GIE);       // Enter LPM0, interrupts enabled

while(1)

{

  while (!(UCA0TXIFG));

  UCA0TXBUF = 0x41; 

}

}

// Echo back RXed character, confirm TX buffer is ready first

#pragma vector=USCIAB0RX_VECTOR

__interrupt void USCI0RX_ISR(void)

{

  while (!(IFG2&UCA0TXIFG));                // USCI_A0 TX buffer ready?

  UCA0TXBUF = UCA0RXBUF;                    // TX -> RXed character

}