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CCS/MSP430FR5994: 16 bit SPI data sync issues

Part Number: MSP430FR5994

Tool/software: Code Composer Studio

I am trying to make spi work with dma to transfer data to the UCAxTXBUF. The issue I am having is that the data loses sync with the clock. It also does not seem to enter the dma ISR. In terms of SPI, I am using the UCA3 bus with a 1.54Mhz bit clock to achieve a continuous 16bit data stream.  I am not sure what I am doing wrong (or even if the MSP430FR5994 can do this). I have attached the code of how I am configuring the SPI and DMA registers. 

    // UCA3 Settings:
    // Master
    // 4 Pin SPI
    // 8 data bits
    // Clock Source: SMCLK (24 MHz)
    // Bit Rate Divider:(for 1.536 MHz)
    // No Modulation
    // MSB First
    // Clock Phase - UCCKPL = 0, UCCKPH = 1
    // MSB first
    UCA3CTLW0 |= UCSWRST;   // Put state machine in reset
    UCA3CTLW0 |= UCCKPH | UCMSB | UCMST | UCMODE_1 | UCSYNC;
    UCA3CTLW0 &= ~(UCCKPL);
    UCA3CTLW0 |= UCSSEL__SMCLK;
    UCA3BRW = 0x11;  //scaling value for clock = 1.536Mhz
    UCA3CTLW0 &= ~UCSWRST;    
    
//DMA3 init config
    char spi_buffer[2] = {0};
    DMACTL1 |= DMA3TSEL_17;   // according to trigger number of UCA3TXIFG
    DMA3CTL = DMADT_4 + DMADSTBYTE + DMASRCBYTE + DMAIE + DMAEN+DMASRCINCR_3+ DMADSTINCR_0;
    __data16_write_addr((unsigned short) &DMA3SA,(unsigned long) spi_buffer);
    __data16_write_addr((unsigned short) &DMA3DA,(unsigned long) &UCA3TXBUF);
    DMA3SZ = 2;
           

This is what I am doing to initialize transfer, I did not include the ISR because it is not relevant. I also noticed that I am unable to enter the ISR using breakpoint in debug mode.

    //To trigger bursts of activity
    UCA3IFG &= ~(UCTXIFG);
    UCA3IFG |= (UCTXIFG);

    spi_buffer[0] = 0x02;
    spi_buffer[1] = 0x01;
    while(1)
    {
        if (!(DMA3CTL & DMAEN))
        {
            DMA3SZ = 2;
            DMA3CTL |= DMAEN;
        }
        if (DMA3CTL & DMAIFG)
        {
            temp = DMA3CTL;
        }

    }
}

Any help would be appreciated, thank you!

  • I'm not quite sure what it means that "the data loses sync with the clock". Are you seeing incorrect bus cycles mid-byte?

    You're using UCMODE=1 with UCSTEM=0.

    1) How is the UCA3STE pin connected/configured? Activity on this pin can cause the master (your) side to freeze. [Ref UG (SLAU367O) Sec 31.3.3.1 and Table 31-1] If you don't need /CS, I suggest UCMODE=0.

    2) See if Erratum USCI50 applies [Ref Errata Sheet (SLAZ681M) p. 12]

  • Bruce McKenney47378 said:
    'I'm not quite sure what it means that "the data loses sync with the clock". Are you seeing incorrect bus cycles mid-byte?

    When I look at the data on a logic analyzer, the data is correct on maybe one instance but tends to drift away from the clock. This means sending 0x1 on the data line shows up as 0x10,0x80 etc. 

    Bruce McKenney47378 said:

    You're using UCMODE=1 with UCSTEM=0.

    I need to use 4 wire SPI as I am trying to convert 4wire SPI to left justified I2S. Setting UCSTEM = 1 stops the output completely. 

    I have referred this TI document to approach this problem. 

    http://www.ti.com/lit/an/slaa449a/slaa449a.pdf

    Thank you so much for your assistance!

  • The AppNote also seems to use UCMODE=0. They don't seem much concerned about /CS (/FS) at all. I think UCMODE=1 will just get in your way.

    I'm not sure what to tell you about your apparent bit-skew. Synchronizing SCLK and MOSI is pretty much Job #1 for the SPI. Do you have a scope trace you could post? Also, are you using the LRCLK counter (attached to SCLK) they mention in Fig 3?

  • Using UCMODE = 0 seemed to fix my issue. Thank you!

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