MSP430F5326: I2C master mode: R/W to R when transmitting address

Part Number: MSP430F5326

Hello,

MSP430F5326 acting as a master, I need to have the r/w bit set to Read while transmitting the address as showed herebelow:

But I only succeeded to have r/w bit at 0.

Here is the code:

    UCB0CTL1 |= UCSWRST;                      /* software reset enabled */
    UCB0CTL0 |= UCMST | UCMODE_3 | UCSYNC ;       /* slave & master adress : 7 bits, single master config, master mode, I2C enabled, synchronous mode */
    UCB0CTL1 = UCSSEL_2 | UCSWRST ;                    /* source slock : SMCLK, USCI logic held during reset state */
    UCB0BR0 = 80; // SPICLK = SMCLK/80  : 100kHz (max 400kHz)
    UCB0BR1 = 0x000;
    UCB0CTL1 &= ~UCSWRST;                      /* clear software reset */

    UCB0I2CSA = slave_adr ;                      // load slave adress
    UCB0CTLW0 |= (UCTR | UCTXSTT);                     // I2C Tx  + start condition
    UCB0IFG &= ~(UCNACKIFG);
    while ((UCB0IFG & UCTXIFG) != UCTXIFG)    /// attente buffer libre
    {
        if ((UCB0IFG & UCNACKIFG) == UCNACKIFG)
        {
            nack = True;
            debug_str("NACK\r\n");
            break;
        }
    }

What am I wrong?

Is there any specific configuration?

Best regards

Mich