MSP430F5529: Logic gates? How do I combine bits to get say P4.7 = (P2.3 AND P2.5)

In general you can't do this. None of the MSP430s (to my knowledge) has the sort of little-logic block  seen in e.g. C2000 CLB or some MCUs from [Other Guys]. The AppNotes I've seen where the authors needed this sort of thing used external logic.

For specific cases, there might be tricks. I would start with the DMA, which can be triggered using a timer match and can copy things from anywhere to anywhere else, including peripheral registers [Ref data sheet (SLAS590N) Table 6-10]. There might also be a trick with the Comparator, though I haven't tried this.

>P2OUT = (BIT3 & BIT5);   // attempt using AND, to get 1 Hz with 4 Hz modulation // fails 

This is a valid C statement -- it takes the result of (0x08 & 0x20)=0 and stores it into P2OUT -- but it doesn't do what you want. To do the logic in software you'll have to spell it out:

>if ((P2IN&BIT3)&&(P2IN&BIT5)) P2OUT |= BIT7; else P2OUT &= ~BIT7;

(For this particular case, where both pins are in the same port, you could use a slightly shorter form, but this is the general case.)

Is the 1Hz enable signal internal or external?

Thank you Bruce. 

I tried pasting that line into the code and compiled it and it ran, but still no AND on the LED. 

The syntax you show is intriguing.  I would not have guessed it.  Are you sure it should work?  I am working solo on this and only have passing familiarly with C.  

My conceptual model for this process is that one writes the code to accomplish a task and the microprocessor has enough switches to wire things up internally the way that gives you the output you want.  

Clearly, there are expected setups that were planned for, the User Guide and the data  sheets have those, but they can't plan for everything. There are too many possibilities.  I would expect a NAND and NOR could be done in software -but making a master slave JK FF is probably not easily done! 

I have seen examples where an 8 bit port can function as a shift register, or an 8 bit ADC, but those come from the way numbers are stored at the hardware level.  
I can of course use external logic.  I have some 4000 series CMOS I can use for this.    I am concerned about the speed and drive level at only 3.3 V, but it will probably work.  I could also do a wired AND and buffer it of course.   


  

You didn't mention an LED before. Where is it? I offered that line of code as an alternative to the one you pointed out. Among other things, it gives you only an instantaneous indicator, not a continuous signal, so it doesn't solve your stated problem.

You could gate the timer output in software -- when you encounter an edge (compare interrupt) on the Enable signal, just stop the timer or set OUTMOD to stop the output pulses. There would be some latency, though in the context of a 1Hz signal a few 10s of microseconds of latency might not be noticed. 

Hello Bruce and thank  you again for your support and kindness. 

I plan to use this AND signal to drive the  LED for a photogate that senses the maximum amplitude of a clock pendulum.   I could drive  the photogate all the time, but it is wasteful of battery.  I want high total efficiency. Just for the challenge. 

I set up the code above so the 1 Hz and the 4 Hz are derived from a CONT mode in the timer, generating toggles of different periods.  I wanted 4 Hz and 1 Hz for this test setup because I can use an LED as a simple indicator of success in the hardware and the software. I can easily see that, and don't need an oscilloscope or any other hardware. These little boards fit in my satchel and it is a minimalist approach to learning how to program them.  

For the actual pendulum clock I will sample at 32 Khz or faster and maintain the amplitude very tightly using the photogate at the maximum amplitude.  A second photogate will ensure the pendulum is at BDC bottom dead center, when pendulum drive is supplied. That will be done infrequently, to allow the pendulum to be free, as much as possible. Drive at BDC affects the period of the pendulum minimally. 

The design is derived from the Hipp Toggle Clock which is one of the early electromechanical clock drives and is elegantly simple.  I can't find a clear enough illustration that I can link to here, but I will try tomorrow.  If you are interested.