Tool/software: Code Composer Studio
I remarked that the UART (working with SMCLK) was too slow. So I tried to have the SMCLK signal as an output on PJ.0. With the oscilloscope, I see that this SMCLK signal is far too slow (25.000Hz instead of the expected 4.000.000Hz). It is the same for MCLK on PJ.1. On the other side ACLK on PJ.2 is OK with 4.096Hz, but it also use directly the LFXT.
I knew that it is only a small error in the declaration, but I couldn't find it.
//Reduced software part, that only gives the "false" output signals on PJ.0 (SMCLK) and on PJ.1 (MCLK), without any UART initialisation
int main(void)
{
WDTCTL = WDTPW | WDTHOLD; // stop watchdog timer
PJSEL0 = BIT4 | BIT5; // Initialize LFXT pins
PM5CTL0 &= ~LOCKLPM5;
//Clock initialisation
CSCTL0_H = CSKEY_H; // Unlock CS registers
CSCTL1 = DCOFSEL_3; // Set DCO to 4MHz
CSCTL2 = SELA__LFXTCLK | SELS__DCOCLK | SELM__DCOCLK;
CSCTL3 = DIVA__8 | DIVS__1 | DIVM__1; // Set all dividers
CSCTL0_H = CSKEY_H; // Unlock CS registers
CSCTL4 &= ~LFXTOFF; // Enable LFXT
do
{
CSCTL5 &= ~LFXTOFFG; // Clear LFXT fault flag
SFRIFG1 &= ~OFIFG;
} while (SFRIFG1 & OFIFG); // Test oscillator fault flag
CSCTL0_H = 0; // Lock CS registers
//Port initialisation: PJ.0: SMCLK, PJ.1: MCLK, PJ.2: ACLK
PJDIR |= 0x01+0x02+0x04;
PJSEL0 |= 0x01+0x02+0x04;
//loop
while(1)
{;}
}
