Hello!
I would like to check if what I'm planning is possible.
F5500 has 2 USCI, A1 and B1.
I would lie to use one as slave and one as master, so I will have to remap port 4 because A1CLK is B1STE and B1CLK is A1STE. So I think I will remap either of the STE to P4.7 or P4.7 in order to have independant STE / CLK. Is this possible (i.e. will it work?).
I can't try now, I'm making the PCB, so it would be nice to know it before getting the PCB done.
I'm thinking about this mapping:
P4.0 : A1CLK (no change)
P4.1 : B1MOSI (no change)
P4.2 : B1MISO (no change)
P4.3 : B1CLK (no change)
P4.4 : A1MOSI (no change)
P4.5 : A1MISO (no change)
P4.6 : B1STE
P4.7 : Whatever, possibly PM_NONE.
By the way, PM_NONE allows me to use it a regular GPIO, right?
Thanks,
Pascal
