MSP430FR5989-EP: MSP430FR5989-EP SPI BUS with 3 MSP430 (1 master, 2 4wire slaves using STE as input for slave select)

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Is there a minimum time between the slave select line going low and when the MSP430 SPI state machine SCLK should starts (in terms of SCLK cycles maybe)?  we have about 5uS.  SCLK is currently 500kHz.

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Yes, according to the datasheet, page 56, table 5.20, that time is 40 ns.

What sort of errors?

An SPI slave on an MSP430 has a difficult time, because (a) an MSP430 isn't very fast and (b) there's no flow control. With a 500kHz clock and back-to-back bytes, the slave has only 16us to respond. (The SCK isn't the problem, rather the back-to-back is.)  DMA can help but it requires a certain amount of prescience. 

The first thing to try is probably to slow down the SPI, --either slowing down the SCK or metering by introducing artificial delays between the bytes.

Hey Carl,

1. I'm not sure what you mean by "how to know STE pin is working as input".  I guess you can wait until the slave is transmitting data and bring the STE pin high to force it to stop. 

STE is not quite the same thing as a standard SS signal, but it may work for your application.  Most applications will end up using 3 wire mode and manually monitoring the SS pin.  I think this description by Jens is pretty good at explaining how this signal works.  https://e2e.ti.com/support/microcontrollers/msp430/f/166/t/251036?SPI-STE-functionality-confusion- 

2. I don't think there is a best-case, just make sure all MSP40s match as you have done.

3. Related to #1, if you end up manually interrupting off this pin, then the application will have an effect on this timing. 

No idea why it would work at 20C and not 25C.  SPI being synchronis means minor timing differences shouldn't affect it.  Have you tried looking at the waveforms with an LSA?  Maybe it's related to the STE behaviour described above. 

Thanks,

JD  

Item 1.  It says some MSP430...  Is the MSP430FR5989-EP one of them?  Where is the list of MSP430 uP that this works for....  That's where that question originated.

New Item.   The problem has been narrowed further.  It seems we can induce failures SPI failure by a weird means that I won't go into.  The results of the failure is left shilfted data at both slaves.   The waveforms for SCLK look good with a FET probe.  So no extra clocks to shift the code, or ringing on the clock edges.

What can cause bit shifts left with regard to operation SPI state machine operation..

Typical working waveforms...

Ch 1 SCLK,  CH 2 MOSI,  Ch 3 MISO,  Ch 4 SS1 (active low) at slave 1 STE

The middle SCLK signals are retries to see if the slave is ready to respond yet.

How is the minimum and maximum response delay between bytes required determined?   Each MSP430 is fed by its own 16MHz crystal oscillator.

SCLK is 500kHz.   Looking for timing things that can cause left shifted bits at the slave in 4 pin slave mode using the STE pin as input.

Current byte spacing is at least 32uS. 

Taking this offline for now, but I'll update this thread once we find a resolution.  

Thanks,

JD