Part Number: MSP430FR2311
Hello Texas Instruments.
I'm using the MSP430FR2311 LaunchPad and I have a very unusual problem.
PORT 2 interruptions are not being triggered.
I wrote the test program below.
I ran the program and tested it with a square wave generator at the inputs from P2.0 to P2.7, one at a time and in combinations. I found that the P2IFG record is always 0.
In the main loop, I put a line to copy P2IN to P1OUT to see if the square wave was being detected correctly and P1 apparently replicates P2.
As I have two LaunchPads, I tested with the other one to see if it is not a hardware problem, but the same occurs.
I was using CCS version 10.0.0.00010. I found another member's post that reported a similar problem, but with CCS8:
https://e2e.ti.com/support/microcontrollers/msp430/f/166/t/692426?MSP430FR2433-Port-2-Interrupt-not-triggering-and-defaulting-to-ISR-Trap
I updated CCS to version 10.1.0.00010 but the problem persisted.
Please if you can help me, I've been stuck on this problem for a few days now.
Thank you for your attention.
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#include <msp430.h>
#include <stdbool.h>
#include <stdint.h>
__interrupt void PORT2_ISR (void);
uint32_t p2_int_cnt[8] = {0, 0, 0, 0, 0, 0, 0, 0};
void main (void){
WDTCTL = WDTPW | WDTHOLD; // Stop watchdog
FRCTL0 = FRCTLPW | NWAITS_1; // 1 wait state for Sys Clk = 16 MHz
__bis_SR_register(SCG0); // disable FLL
CSCTL3 |= SELREF__REFOCLK; // Set REFO as FLL reference source
CSCTL0 = 0; // clear DCO and MOD registers
CSCTL1 &= ~(DCORSEL_7); // Clear DCO frequency select bits first
CSCTL1 |= DCORSEL_5; // Set DCO = 16MHz
CSCTL2 = FLLD_0 + 487; // set to fDCOCLKDIV = (FLLN + 1)*(fFLLREFCLK/n) = (487 + 1)*(32.768 kHz/1) = 16 MHz
__delay_cycles(3); // wait 3 cycles
__bic_SR_register(SCG0); // enable FLL
while (CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1)); // FLL locked
CSCTL4 = SELA__REFOCLK | SELMS__DCOCLKDIV;
PM5CTL0 &= ~LOCKLPM5;
P1DIR = 0xFF; // P1 all pins output
P1SEL0 = 0x00; // P1 all pins GPIO
P1SEL1 = 0x00;
P1OUT = 0x00;
P1REN = 0X00;
P2DIR = 0x00; // P2 all pins input
P2SEL0 = 0x00; // P2 all pins GPIO
P2SEL1 = 0x00;
P2OUT = 0x00;
P2REN = 0X00;
P2IES = 0x00; // P2 all pins rising edge interrupt
P2IFG = 0; // Clear all P2 interrupt flags
P2IE = 0x00;
P2IE |= BIT0; // Enable P2.0 interrupt
// P2IE |= BIT1; // Enable P2.1 interrupt
// P2IE |= BIT2; // Enable P2.2 interrupt
// P2IE |= BIT3; // Enable P2.3 interrupt
// P2IE |= BIT4; // Enable P2.4 interrupt
// P2IE |= BIT5; // Enable P2.5 interrupt
// P2IE |= BIT6; // Enable P2.6 interrupt
// P2IE |= BIT7; // Enable P2.7 interrupt
__bis_SR_register (GIE); // General interrupt enable
while (true){
P1OUT = P2IN; // Copy P2 inputs to P1 output
}
}
#pragma vector = PORT2_VECTOR
__interrupt void PORT2_ISR (void){
switch(__even_in_range(P2IV, P2IV__P2IFG7)){
case P2IV__NONE:
break;
case P2IV__P2IFG0:
p2_int_cnt[0]++;
break;
case P2IV__P2IFG1:
p2_int_cnt[1]++;
break;
case P2IV__P2IFG2:
p2_int_cnt[2]++;
break;
case P2IV__P2IFG3:
p2_int_cnt[3]++;
break;
case P2IV__P2IFG4:
p2_int_cnt[4]++;
break;
case P2IV__P2IFG5:
p2_int_cnt[5]++;
break;
case P2IV__P2IFG6:
p2_int_cnt[6]++;
break;
case P2IV__P2IFG7:
p2_int_cnt[7]++;
break;
default:
break;
}
}
