REGARDING ADC SAMPLING MODES

Srikant Avasarala said:

why I cannot modify the ADC12 register values when the ENC = 1 ?

That's simple. All setting which will alter the inner behavior of the ADC cannot be altered when conversions are enabled. Altering them would do changes in teh progress of sampling which will possibly make any result of an ongoing or scheduled conversion more or less random and not reliable. Therefore these bits are locked if the ADC is in conversion mode.

Or with other words: these switches must be set before starting the engine.

Srikant Avasarala said:

what is the significance of the Sync block in ADC12 module ( and t_sync)

The conversion itself needs to be synced to the conversion clock. The SAMPCON signal, however, is not necessarily in sync with the conversion clock. It may be clocked by a timer whcih may be clocked by a different clock) or by software (whcih is synced to MCLK but not necessarily to the used conversion clock and definitely not synced to ADC12OSC) or may be trigered by an external signal (and therefore not synced with anything in the MSP).
t_sync is not a necessary time, but a resulting time caused by the fact that SAMPCON will not necessarily be synced with ADC12CLK. So it is the resulting difference of the falling edge of SAMPCON (however it might be generated/controlled) and the next rising edge of ADC12CLK.
The datasheet does not list a minimum t_sync , so it seems that it can be 0 if SAMPCON happens to exactly match the raising edge of ADC12CLK. (if SAMPCON is generated by ADC12CLK, then it's possibly always 1/2 ADC12CLK)

About pulse and extended sampling mode:

Pulse sampling mode means that you trigger the start of a conversion with a pulse and samplign will follow th egiven parameters: sample time according to SHTx, counted by ADC12CLK, then x+1 cycles for the conversion. THen the next pulse can come. If you trigger it too fast, the pulse will be simply ignored.
If you need conversion in equal distances, don't care for the samplign time too much, use ADCOSC for the timing, this is the way to go. You trigger, and some time later you'll get a result. You can trigger from a timer ISR, or just when you want a result. It's easy and straight.

If you neeed more precision about the very moment of starting the conversion, or want to maximize the sampling time, so you have a low-pass or give the signal source time to recover from the inrush current into the sampling capacitor (if the source is high-impedance), the extended sampling mode gives youmore control.

Here you 'open the gates' manually, and the moment you close the input, sampling starts. This allows you to use a fast conversion clock(sort conversion time and therefore very low degradation of the sampled voltage) in conjunction with very long sampling times (extreme low-pass). In this mode, however, you cannot open the input whiel the conversion isn't finished. This will make your conversion result invalid and this is flagged by ADCTOV. The typical configuration for this is to use the timer controlled triggering in conjunction with a double-action capture mode. Hereone edge of the CCR signal starts sampling, the other edge ends sampling and starts converting.

So basically, if you want to have the ADC12 either sampling or converting, you use a timer to control the S&H unit in extended samplign mode. If you just want to trigger a conversion and get a result some time later, you use the pulse mode.

Which of the two modes to use depends on your overall conditions and there is no definitive either/or but rather a floating shift from one to the other.

There is, however,  a 'third mode' that combines both: configure ACLK/SMCLK or an external clock so it will exactly do the required number of cycles for pulse mode in the time you have for one conversion, then let the ADC run in continuous mode, clocked by this clock. You'll get a constant stream of conversions. It is, however, a bit difficult to get the proper frequency, since the numbe rof cycles for conversions is always odd and not a power of two while the number of cycles for SHT is even and (sort of) a power of two).
E.g. if you want 5k conversion/s with 12 bit and a SHT_16, you need a 154kHz clock (5000*(16+13)) and the sampling time (settling time for the input) is 110µs. Then you'll get one conversion result every 1/5000s with the ADC running in continuous mode and no more triggers needed than the very first.