Part Number: MSP430FR2311
Hi,
My code is supposed to generate a single pulse when sine is crossing 0. To test it I am using sine that has DC offset 1.65V halve of 3.3V. I compare it with 1/2 VCC internal refernce for comparator.The sine amplitude is 35 mV. When I monitor P1.0 output I see that several pulses are generated instead of one. If i increase sine amplitude the number of pulses decreases but still there are several instead of one. I presume that might be due to the noise that is on 1/2 VCC reference and sine noise. I added filtering but it did not help. Is there anything else to clear it up?
thanks vadim
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#include <msp430.h>
int main(void)
{
WDTCTL = WDTPW | WDTHOLD; // Stop WDT
// Configure GPIO
P1OUT &= ~BIT0; // Clear P1.0 output latch for a defined power-on state
P1DIR |= BIT0; // Set P1.0 to output direction
// Configure Comparator input & output
P1SEL0 |= BIT1; // Select eCOMP input function on P1.1/C1
P1SEL1 |= BIT1;
P2DIR |= BIT0;
P2SEL1 |= BIT0; // Select CPOUT function on P2.0/COUT
PM5CTL0 &= ~LOCKLPM5; // Disable the GPIO power-on default high-impedance mode
// to activate previously configured port settings
// Configure reference
PMMCTL0_H = PMMPW_H; // Unlock the PMM registers
PMMCTL2 |= INTREFEN; // Enable internal reference
while(!(PMMCTL2 & REFGENRDY)); // Poll till internal reference settles
// Setup eCOMP
CPCTL0 = CPPSEL0; // Select C1 as input for V+ terminal
CPCTL0 |= CPNSEL1 | CPNSEL2; // Select DAC as input for V- terminal
CPCTL0 |= CPPEN | CPNEN; // Enable eCOMP input
CPCTL1 |= CPIIE | CPIE; // Enable eCOMP dual edge interrupt
CPDACCTL |= CPDACEN; // Select VCC as reference and enable DAC
CPDACDATA |= 0x0020; // CPDACBUF1=VCC *32/64
CPCTL1 |= CPEN; // Turn on eCOMP, in high speed mode
CPCTL1 |= CPFLT_1;
CPCTL1 |= CPFLTDLY_3;
__bis_SR_register(LPM3_bits | GIE); // Enter LPM3
__no_operation(); // For debug
}
// eCOMP interrupt service routine
#pragma vector=ECOMP0_VECTOR
__interrupt void ECOMP0_ISR(void)
{
switch(__even_in_range(CPIV, CPIV__CPIIFG))
{
case CPIV__NONE:
break;
case CPIV__CPIFG:
P1OUT = BIT0;
__delay_cycles(100);
P1OUT = ~BIT0;
break;
case CPIV__CPIIFG:
P1OUT = BIT0;
__delay_cycles(100);
P1OUT = ~BIT0;
break;
default:
break;
}
}
*****
