- Ask a related questionWhat is a related question?A related question is a question created from another question. When the related question is created, it will be automatically linked to the original question.
Original question:
Hi team,
Our customer is looking for SPI-to-I2C bridge device. Since it does not seem TI have this bridge chip, we will plan to introduce MSP430FR2310.
Connection structure is, "External CPU---> [SPI/Slave : MSP430 :I2C/Master] -->ROM"
this means, MSP430’s SPI is “Slave”, MSP430’s I2C is “Master”.
Would you think that customer is able to do this implementation? Is there any concern for this implementation?
MSP430FR2310 is supporting I2C 400KHz, however, I’m not sure this device is supporting max of Serial clock for SPI, Could you elaborate it, please? My concern is buffer-overflow at this time.
Best regards,
Miyazaki
Hi Miyazaki,
>> Would you think that customer is able to do this implementation?
I think this application is suitable for FR2310
>> Is there any concern for this implementation?
There is no DMA on FR2310. I2C speed and SPI speed are not the bottleneck. data transmission by CPU should be considered.
>> I’m not sure this device is supporting max of Serial clock for SPI
Please check page 33 of MSP430FR231x Mixed-Signal Microcontrollers datasheet (Rev. E)
max fucxclk is ~3MHz.
Thanks!
**Attention** This is a public forum
