MSP430G2553: [ISSUE!!] Using MSP430 Timer1_A3 in UP/DOWN mode for PWM control of Half-Bridge Inverter

From the manual:  "It is recommended to stop the timer before modifying its operation (with exception of the
interrupt enable, and interrupt flag) to avoid errant operating conditions."

I have included stoppage of the timer, however I am still seeing unwanted behavior. Below is the updated interrupt code. Is this a common issue when operating the G2553 at higher than 1 MHz DCO clock?

/*** Timer_1_A3 Interrupt Service Routine ***/
#pragma vector =unused_interrupts
__interrupt void Timer1_A3_ISR (void)
{
    z++;                                // Increment Counter
    if (z == 5)                         // Counter z == 5, (~200 us); 5 sawtooth cycles, (320 *5) @ 8 MHz
    {
        TA1CTL |= MC_0 + TACLR;         // Stops Timer 1 A3 and clears timer
        n++;                            // increment look-up table index
        if (n >=84)                     // check if index value is outside array length
        {n=0;}                          // If true, reset index value
        DUTY_1 = Sin_lookup[n];         // Change look-up table value
        DUTY_2 = Sin_lookup[n]-5;       // Change look-up table value - ~600 ns dead time
        TA1CCR2 = DUTY_2;               // TA1CCR1 PWM Duty Cycle updates
        TA1CCR1 = DUTY_1;               // TA1CCR2 PWM Duty Cycle updates
        TA1CTL |= TASSEL_2 + ID_0 + MC_3 + TAIE;      // SMCLK, Divided by 1, Up/Down Mode (Counts to TA1CCR0), & enable interrupts
        z = 0;                          // Reset counter
    }
    TA1CTL &= ~TAIFG;                   // Clear interrupt flag
}

Attached is an oscilloscope capture with the updated code.

Is there some reason why you don't use TA1IV to verify that you have a valid interrupt and clear it?

I suspect that the original code had a race condition. For small values from the sine lookup table the counter could pass that value before you updated the registers. Or conversely it could toggle based on the old value before you set the new one. A hazard when running the timer at such a high clock speed.

Thanks for the help David, I am unsure in how to implement that using the TA1IV. Would I use a switch() fcn. I am currently using a #pragma vector= unused interrupts because I could not find a interrupt service routine for Timer 1 A3. Could you provide an example if possible. I would greatly appreciate it.

After looking further into the family guide I believe I may have figured out the interrupt check using TA1IV. The code is shown below. I will try this out and see if it makes a difference.

/*** Timer_1_A3 Interrupt Service Routine ***/
#pragma vector =unused_interrupts
__interrupt void Timer1_A3_ISR (void)
{
 switch (TA1IV)
 {
  case TA1IV_NONE:
      break;
  case TA1IV_TACCR1:
      break;
  case TA1IV_TACCR2:
      break;
  case TA1IV_TAIFG:                                 // Interrupt due to Timer overflow interrupt flag
  {
      z++;                                // Increment Counter
      if (z == 5)                         // Counter z == 5, (~200 us); 5 sawtooth cycles, (320 *5) @ 8 MHz
          {
           TA1CTL |= MC_0 + TACLR;         // Stops Timer 1 A3 and clears timer
           n++;                            // increment look-up table index
           if (n >=84)                     // check if index value is outside array length
             {n=0;}                          // If true, reset index value
           DUTY_1 = Sin_lookup[n];         // Change look-up table value
           DUTY_2 = Sin_lookup[n]-5;       // Change look-up table value - ~600 ns dead time
           TA1CCR2 = DUTY_2;               // TA1CCR1 PWM Duty Cycle updates
           TA1CCR1 = DUTY_1;               // TA1CCR2 PWM Duty Cycle updates
           TA1CTL |= TASSEL_2 + ID_0 + MC_3 + TAIE;      // SMCLK, Divided by 1, Up/Down Mode (Counts to TA1CCR0), & enable interrupts
           z = 0;                          // Reset counter
          }
       TA1CTL &= ~TAIFG;                   // Clear interrupt flag
       break;
  }
  default:
       break;
  }
}

>        TA1CTL |= MC_0 + TACLR;         // Stops Timer 1 A3 and clears timer

This doesn't stop the timer. To do that, you should

>       TA1CTL = (TA1CTL & ~MC) | TACLR;         // Stops Timer 1 A3 and clears timer

I'm also not sure you want to use TACLR. Stopping the timer is already going to cause a small aberration in the timing, and resetting the counter will make the aberration that much bigger.

Also, your goal should be to update the CCR as close to the beginning of the cycle as you can manage. To this end, I suggest you update the CCR as the first thing, and then do your bookkeeping (preparation for next time) afterward, while the counter is counting.

I've tried to stop the timer differently, removed the timer clear, and rearranged the order of the lines to prioritize updating CCR. However, I am still getting an undesired output. Attached is the updated interrupt service routine as well as an o-scope image of the output.

/*** Timer_1_A3 Interrupt Service Routine ***/
#pragma vector =unused_interrupts
__interrupt void Timer1_A3_ISR (void)
{
 switch (TA1IV)
 {
  case TA1IV_NONE:
      break;
  case TA1IV_TACCR1:
      break;
  case TA1IV_TACCR2:
      break;
  case TA1IV_TAIFG:                       // Interrupt due to Timer overflow interrupt flag
  {
      if (z == 5)                         // Counter z == 5, (~200 us); 5 sawtooth cycles, (320 *5) @ 8 MHz
          {
           TA1CTL &= ~MC_3;                // Stops Timer 1 A3 and clears timer
           TA1CTL |= MC_0;                 // Sets TA1CTL to STOP mode (MC_0)
           TA1CCR2 = Sin_lookup[n]-5;               // TA1CCR1 PWM Duty Cycle updates
           TA1CCR1 = Sin_lookup[n];               // TA1CCR2 PWM Duty Cycle updates
           TA1CTL |= TASSEL_2 + ID_0 + MC_3 + TAIE;      // SMCLK, Divided by 1, Up/Down Mode (Counts to TA1CCR0), & enable interrupts
           z = 0;                          // Reset counter
           n++;                            // increment look-up table index
           if (n >=84)                     // check if index value is outside array length
             {n=0;}                        // If true, reset index value
          }
       z++;                                // Increment Counter
       TA1CTL &= ~TAIFG;                   // Clear interrupt flag
       break;
  }
  default:
       break;
  }
}
 

It looks like you're still losing the race, i.e. by the time you update CCR2, the timer is already past it.

The smallest value I see in your table is 35, so your deadline for updating CCR2 (or stopping the timer) is 35-5=30 clocks. Estimate 15 clocks to get into the ISR, that gives you 15 clocks to get to the critical step, which is only 3-4 instructions. This timing is very tight.

1) Try the optimizer, if you haven't already. That might give you back the few extra clocks you need.

2) I'm going to respectfully disagree with David and say you shouldn't bother to check the IV -- you know why you're here, and it costs you extra CPU clocks in a critical path. Put a comment in a prominent spot at the top to the effect that "TAIFG is the only reason we get here".

3) Consider dispensing with the interrupt entirely, and poll for TAIFG up in main(). Your entire cycle is only 320 clocks, and you're probably using up half of that in your bookkeeping, i.e. your program won't be able to do much else anyway.

The best way to attack this is to slow down the timer clock. Get it working with a slower clock and then work on making it run at the desired rate.