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Original question:

MSP430F5419A: MSP430F5419A I2C glitch / spike issue

Compiler/MSP430F5419A: MSP430F5419A

Swarna latha
Prodigy 50 points
Part Number: MSP430F5419A

Tool/software: TI C/C++ Compiler

Hi Team,

We are using MSP430F5419A and during some conditions, we will put it HIBERNATE mode by doing the below method.

#if defined __MSP430_HAS_UCS__
// As per the 249 code add clock configuration
// Set to default
// Lowest current consumtion for LF
UCSCTL6 = XT2OFF | XT1DRIVE_0 | XCAP_3 | SMCLKOFF; // 12 pF load
UCSCTL0 = 0; // Make sure we do not overclock...
UCSCTL1 = DCORSEL_2; // Worst case range 6.0 - 23.7 MHz
UCSCTL2 = FLLD_1 | 31; // Multiply 244 times ~7995392 Hz - 276 ppm from 8 MHz
UCSCTL4 = SELA__XT1CLK | SELS__DCOCLKDIV | SELM__DCOCLKDIV;

UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
// Worst-case settling time for the DCO when the DCO range bits have been
// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
// UG for optimization.
// 32 x 32 x 8 MHz / 32,768 Hz = 250000 = MCLK cycles for DCO to settle
__delay_cycles(500000);

// Loop until XT1,XT2 & DCO fault flag is cleared
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
// Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
}while (SFRIFG1&OFIFG); // Test oscillator fault flag
#elif defined __MSP430_HAS_BC2__
BCSCTL1 = XT2OFF + RSEL0 + RSEL1 + RSEL2; // DCO default
DCOCTL = DCO0 + DCO1; // DCO default
BCSCTL2 = 0;
#else
BCSCTL2 = DIVM_3; // BCL5 chip errate workaround
BCSCTL1 = XT2OFF + RSEL2; // DCO default
BCSCTL2 = 0; // BCL5 chip errate workaround
DCOCTL = DCO0 + DCO1; // DCO default
#endif

Is this code fine, to put the MSP in low power mode?

or do we have to do the below step also ?

(__bis_SR_register( __SR_GIE \
| __SR_CPU_OFF \
| __SR_SCG0 \
| __SR_SCG1 \
| __SR_OSC_OFF))

Please confirm.

Thanks & Regards,

swarna.N

  • 0
    TI__Guru 68141 points

    sHi Swarna,

    Yes. 

    Also, In case you weren't aware, there are pre-defined "intrinsics" that you can use.  They are located in your device's ".h" header file.

    i

  • 0 in reply to Dennis Lehman
    Prodigy 50 points

    Hi,

    Thanks for the response.

    yes, I checked those functions which will put the MSP in low power mode ,

    In our project, I see this part of the code, not sure if this code will really push the MSP to low power mode?

    Can you please confirm.

    The below code will enable MSP to low power mode?

    #if defined __MSP430_HAS_UCS__
    // As per the 249 code add clock configuration
    // Set to default
    // Lowest current consumtion for LF
    UCSCTL6 = XT2OFF | XT1DRIVE_0 | XCAP_3 | SMCLKOFF; // 12 pF load
    UCSCTL0 = 0; // Make sure we do not overclock...
    UCSCTL1 = DCORSEL_2; // Worst case range 6.0 - 23.7 MHz
    UCSCTL2 = FLLD_1 | 31; // Multiply 244 times ~7995392 Hz - 276 ppm from 8 MHz
    UCSCTL4 = SELA__XT1CLK | SELS__DCOCLKDIV | SELM__DCOCLKDIV;

    UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
    // Worst-case settling time for the DCO when the DCO range bits have been
    // changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
    // UG for optimization.
    // 32 x 32 x 8 MHz / 32,768 Hz = 250000 = MCLK cycles for DCO to settle
    __delay_cycles(500000);

    // Loop until XT1,XT2 & DCO fault flag is cleared
    do
    {
    UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
    // Clear XT2,XT1,DCO fault flags
    SFRIFG1 &= ~OFIFG; // Clear fault flags
    }while (SFRIFG1&OFIFG); // Test oscillator fault flag
    #elif defined __MSP430_HAS_BC2__
    BCSCTL1 = XT2OFF + RSEL0 + RSEL1 + RSEL2; // DCO default
    DCOCTL = DCO0 + DCO1; // DCO default
    BCSCTL2 = 0;
    #else
    BCSCTL2 = DIVM_3; // BCL5 chip errate workaround
    BCSCTL1 = XT2OFF + RSEL2; // DCO default
    BCSCTL2 = 0; // BCL5 chip errate workaround
    DCOCTL = DCO0 + DCO1; // DCO default
    #endif

    Thanks & Regards,

    Swarna.N

  • 0 in reply to Swarna latha
    TI__Guru 68141 points

    Hi Swarna,

    No.  The section of code you are showing only configures the system clocks.  You do that first in your code, then later you put the CPU into one of the LPM modes using the intrinsics.

    Here is example code from the selection of MSP430F5419A examples in the TI Resource Explorer.

    example.c
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    int main(void)
    {
    WDTCTL = WDTPW+WDTHOLD; // Stop WDT
    P7SEL |= 0x03; // Select XT1
    UCSCTL6 &= ~(XT1OFF); // XT1 On
    UCSCTL6 |= XCAP_3; // Internal load cap
    // Loop until XT1,XT2 & DCO stabilizes
    do
    {
    UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
    // Clear XT2,XT1,DCO fault flags
    SFRIFG1 &= ~OFIFG; // Clear fault flags
    }while (SFRIFG1&OFIFG); // Test oscillator fault flag
    UCSCTL6 &= ~(XT1DRIVE_3); // Xtal is now stable, reduce drive
    // strength
    P1OUT = 0x00;
    P2OUT = 0x00;
    P3OUT = 0x00;
    P4OUT = 0x00;
    P5OUT = 0x00;
    P6OUT = 0x00;
    P7OUT = 0x00;
    P8OUT = 0x00;
    P9OUT = 0x00;
    P10OUT = 0x00;
    P11OUT = 0x00;
    PJOUT = 0x00;
    P1DIR = 0xFF;
    P2DIR = 0xFF;
    P3DIR = 0xFF;
    P4DIR = 0xFF;
    P5DIR = 0xFF;
    P6DIR = 0xFF;
    P7DIR = 0xFF;
    P8DIR = 0xFF;
    P9DIR = 0xFF;
    P10DIR = 0xFF;
    P11DIR = 0xFF;
    PJDIR = 0xFF;
    __bis_SR_register(LPM3_bits); // Enter LPM3
    __no_operation(); // For debugger
    }
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

  • 0 in reply to Dennis Lehman
    TI__Guru 68141 points

    Hi Swarna,

    I'll assume you were able to resolve your issue so I will go ahead and close this thread.
    If this isn’t the case, please click the "This did NOT resolve my issue" button and reply to this thread with more information.
    If this thread locks, please click the "Ask a related question" button and in the new thread describe the current status of your issue and any additional details you may have to assist us in helping to solve your issues.


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