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MSP430F67791A: Difference between SD24's group CH Conversion and single CH Conversion

O.H
Mastermind 6650 points
Part Number: MSP430F67791A


Hi experts,

My customers is evaluating the SD24 and the conversion result is different for one channel (CH4) than the other channels.
I would appreciate any information you can provide.

Q: When I perform A/D conversion with CH4 and other channels at the same time, the result is about 0.3% larger than the result when I performed A/D conversion with CH4 alone.
Is the above behavior expected?

We are comparing a pattern in which CH4 is operated simultaneously with other channels (CH1, CH2, CH3 and CH6 grouped together and operated by continuous conversion) and a pattern in which CH4 is operated independently by continuous conversion.

If the above information is not enough, could you please tell us what information we should check?
(Register settings are being checked.)

Best regards,
O.H

  • 0
    TI__Expert 7365 points

    Hi O.H.,

    Is there a possibility that the signal is varying slightly in time and the conversion start occurs at different times when it is separate vs. group setting? If you are using SW to start the conversion, there might be a delay in terms of when the conversion starts with the single mode vs. starting with the channels that are in the group? How is the "Start of conversion" controlled? The relevant register configuration bits are SD24SCSx in SD24BCCTLx register. This is in 29.3.7 SD24BCCTLx Register of the user's guide (www.ti.com/.../slau208).

    Srinivas

  • 0 in reply to Srinivas Lingam
    Mastermind 6650 points

    Hi Srinivas,

    Thank you for your reply.
    Sorry. There was an error in the previous information.Here is the information we got from the customer.

    When comparing the case of "CH4 acting alone" and the case of "CH4 acting alone + CH1/2/3/6 acting as a group", the conversion result of CH4 in the case of "CH4 acting alone + CH1/2/3/6 acting as a group" is larger by about 0.3%.
    CH4 starts conversion with SD24SCS=000, SD24SC of SD24BCCTL4.
    CH1/2/3/6 are starting conversions with SD24SCS=100 and SD24GRP0SC of SD24BCTL1.
    (All the conversions are performed in Continuous Mode.)

    They took 10 times the data sampled every 61us for four 50 Hz sine wave cycles.
    The result is that the average of the maximum/minimum A/D values of CH4 for "CH4 operating alone + CH1/2/3/6 operating in groups" is slightly larger.

    Srinivas Lingam said:
    Is there a possibility that the signal is varying slightly in time and the conversion start occurs at different times when it is separate vs. group setting? If you are using SW to start the conversion, there might be a delay in terms of when the conversion starts with the single mode vs. starting with the channels that are in the group? How is the "Start of conversion" controlled? The relevant register configuration bits are SD24SCSx in SD24BCCTLx register. This is in 29.3.7 SD24BCCTLx Register of the user's guide (www.ti.com/.../slau208).

    The signal is input as a sine wave. Since the timing for starting conversion is arbitrary, it may be different between single operation and group operation.
    There is no possibility of a delay in the timing of the start of conversion.
    The following table shows the set values of the registers during operation.

    "CH4 acting alone"
    SD24BCCTL1=0x0058
    SD24BCCTL2=0x0059
    SD24BCCTL3=0x0058
    SD24BCCTL4=0x0051
    SD24BCCTL6=0x0059

    "CH4 acting alone + CH1/2/3/6 acting as a group"
    SD24BCCTL1=0x0059
    SD24BCCTL2=0x0059
    SD24BCCTL3=0x0059
    SD24BCCTL4=0x0051
    SD24BCCTL6=0x0059

    Based on the additional information, is this behavior expected?
    (Is a difference of about 0.3% expected for a device?)

    Best regards,
    O.H

  • 0 in reply to O.H
    TI__Expert 7365 points

    Hi O.H.,

    O.H said:
    There is no possibility of a delay in the timing of the start of conversion.

    How is this ensured? Is the conversion start triggered on a timer to ensure the timing is exactly the same in both cases?

    O.H said:
    (Is a difference of about 0.3% expected for a device?)

    If the timing is precisely controlled for both scenarios, this should not occur.

    For a 50 Hz signal, a 0.3% error is approximately 200 clock cycles (25 MHz CPU) difference in the conversion start time. Is there anything in the SW that makes this possible?

    Srinivas

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