CCS v4.2.1 trouble with program load, CCS crash

Working with an MSP430F5438 (not A), I've had a reasonable dev experience with only the occassional CCS instability.    SPI, I2C, drivers for DS3231, AT45DB041 and UART at 9600 with the default (Power on settings) for the UCS.

The clock system (UCS) has now been setup for 5.76MHz MCLK and SMCLK.    Since setting this up (with some help on the e2e forum), I've had a worsening CCS experience.

I need to power cycle the board, or I can't load a program.    There are times (such as now) where no matter what I seem to do - exit and restart CCS, reboot my PC, power cycle the board, disconnect and reconnect the TI USB FET, I can't talk to my board.   

Worse, I've been getting CCS crashes.    Sometimes I get the JVM dump below, sometimes CCS just exits when i hit "Debug Active Target"

I pasted my clock setup code below - maybe one of the bits in one of the many registers does something to the JTAG settings???

I'm going to shutdown my PC, Reboot, reconnect the USB FET, Power on the Board, Start Eclipse in hopes I can see the one edit I did an hour ago....   Any help would be appreciated, or pointers to workarounds that take less time.

Thanks

void msp430_clock_init(void)
{
 UINT16 timeout = 60000;

//                MSP430F5438 (not A)
//             -----------------
//        /|\ |              XIN|-
//         |  |                 | 32kHz
//         ---|RST          XOUT|-
//            |                 |
//            |            P1.6 |--> SMCLK = 5.76MHz
//            |                 |

 WDTCTL = WDTPW + WDTHOLD;                 // Stop watchdog timer

 // for debug, put SMCLK out on P1.6
 P1SEL |= 0x40; // select SMCLK output special func

 // Initialize LFXT1
 P7SEL |= 0x03;                             // Select XT1
 UCSCTL6 &= ~(XT1OFF);                      // XT1 On
 UCSCTL6 |= XCAP_3;                         // Internal load cap

 // Loop until XT1 fault flag is cleared
 do
 {
  UCSCTL7 &= ~XT1LFOFFG;                  // Clear XT1 fault flags
 } while (UCSCTL7 & XT1LFOFFG);                // Test XT1 fault flag
 
 
 
 

 // fDCO(3,0)  DCO frequency (3, 0)  DCORSELx = 3, DCOx = 0,  MODx = 0 0.64  1.51 MHz
 // fDCO(3,31) DCO frequency (3, 31) DCORSELx = 3, DCOx = 31, MODx = 0 6.07 14.0 MHz

 // Initialize DCOCLK to 5.76MHz  (good for SMCLK to gen baud rates 115200, 38400, 9600
 __bis_SR_register(SCG0);                   // Disable the FLL control loop
 UCSCTL0 = 0x0000;                          // When FLL selected,  DCOx, MODx are adjusted automatically by FLL (p67 of MSP430F5xxx family UG)
 UCSCTL1 = DCORSEL_3;                       // Set DCORSELx=3, 1.9usec with FLL off
 
 // lets see what happpens when FLL stays disabled (__bis_SR_register(SCG0);) SMCLK = 500Khz (was 1MHz) before DCORSEL_3
 // FLL off, DCORSEL_1 = 125Khz
 // FLL off, DCORSEL_1 = 250Khz
 // FLL off, DCORSEL_3 = 500Khz
 // FLL off, DCORSEL_4 = 1000Khz (900 ns)
 // FLL off, DCORSEL_5 = 2000Khz (500 ns)
 // FLL off, DCORSEL_6 = 3000Khz (350 ns)
 // FLL off, DCORSEL_7 = 6000Khz (150 ns)
           
 __bic_SR_register(SCG0);                   // Enable the FLL control loop
            
           
            // TODO: bit.0 is modulation, set to enable (not sure)
 //bit.12-14 are FLL loop div, 000=1, 001=/2, 010=/4
 // 0b 0 011 000 <n nnnn nnnn>
 //UCSCTL2 = FLLD_1 + 175;                     // Set DCO Multiplier for 5.76MHz 
                                             // (N + 1) * FLLRef = Fdco
                                             // (175 + 1) * 32768 = 5.76MHz  5767168
                                             // Set FLL Div = fDCOCLK/2
    //UCSCTL2 = FLLD_2 + 100;     // 600 ns
    //UCSCTL2 = 0x3000 + 100;     // 825 ns
    //UCSCTL2 = FLLD_3 + 100;     // 825 ns
    //UCSCTL2 = FLLD_2 + 176;     // 400 ns
    //UCSCTL3 = FLLD_3 + 176;     // 1.8 ua
    //UCSCTL2 = FLLD_2 + 352;     // 400 ns (same as 176, weird)
    //UCSCTL2 = FLLD_1 + 176;     // 350 ns
    //UCSCTL2 = FLLD_1 + 0;      // 1.8 us
    //UCSCTL2 = FLLD_1 + 500;     // 200 ns
    //UCSCTL2 = FLLD_1 + 511;     // 200 ns
    //UCSCTL2 = 0x0000 + 511;     // 120 ns
    //UCSCTL2 = 0x0000 + 300;      // 200 ns
    //UCSCTL2 = 0x0000 + 405;      // 150 ns
    //UCSCTL2 = 0x0000 + 355;      // 175 ns (with some dither)
    UCSCTL2 = 0x0000 + 179;      // 175 = 5.632 Mhz (Tek TDS2024B), 176 = 5.664 Mhz, 177=5.696 Mhz, 178 =  5.73x Mhz, 179 = 5.760
 //FLLREFDIV=bit.0-2, FLLREFCLK=bit.4-6=000 (XT1), bit.0-2 000=/1, 001=/2, 010=/4, 011=/8, 100=/12, 101=/16
 UCSCTL3 = 0x0000;       // bit.4-6 FLLREFCLK SELREF /1
 //UCSCTL3 = 0x0001;       // bit.4-6 FLLREFCLK SELREF   /2

 // Worst-case settling time for the DCO when the DCO range bits have been
 // changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
 // UG for optimization.
 // 32 x 32 x 5.76 MHz / 32,768 Hz = 180000 = MCLK cycles for DCO to settle (wow)
 //for(indx=0; indx<3; indx++)
 // __delay_cycles(60000);
 
 
 //ACLK src = bit.8-10, SMCLK src = bit.4-6, MCLK src = bit.0-2
    //000 XT1CLK UCSCTL4_L Bits 6-4
    //001 VLOCLK
    //010 REFOCLK
    //011 DCOCLK
    //100 DCOCLKDIV
    //101 XT2CLK when available, otherwise DCOCLKDIV
 // 0b 0000 0001 0011 0010   XTQ MCLK=DCOCLK, SMCLK=DCOCLK, ACLK=REF0CLK
 UCSCTL4 = 0x0132;  // MCLK=DCOCLK, SMCLK=DCOCLK, ACLK=REF0CLK
 
 UCSCTL5 = 0x0000;  // ACLK src divider at pin, ACLK src divider, SMCLK src divider, MCLK src divider

 UCSCTL6_L |= XT1DRIVE1_L+XT1DRIVE0_L; // Highest drive setting for XT1 startup
 
 __bic_SR_register(SCG0);                   // Enable the FLL control loop

 P1OUT |= BIT3;       // DEBUG bit
 while ((SFRIFG1 & OFIFG) && timeout--) // check OFIFG fault flag
 {  
  P1OUT &= ~BIT3;      // DEBUG bit   
  UCSCTL7 &= ~(DCOFFG + XT1LFOFFG + XT1HFOFFG + XT2OFFG); // Clear OSC flaut Flags fault flags
  SFRIFG1 &= ~OFIFG;           // Clear OFIFG fault flag
  P1OUT |= BIT3;
 }

 // it timeout occurs, hang here and wiggle status bit
 while(timeout == 0)
 {
  P1OUT |= BIT3;
  P1OUT &= ~BIT3;
 }

}