MSP430FR5994: silicon errata for older revisions

Hi Tomas,

Can you tell me which bug in EERATA you are concerned about? I think the latest version should include all the information about bug.

Thanks!

Best Regards

Johnson

Hi Johnson,
I was doing some timing tests on MSP430FR5994 and I have found the cycles counts of some instructions (in some conditions) don't agree with documentation.
I have checked the user's guide SLAU367P, the errata SLAZ681M and I haven't found any description of these deviations.

1) jump instructions take 3 cycles in some condition
I have found the thread "Cycle timing for jump on CPUXV2 chips" for MSP430F5xx which meets this case.

L1   xor.b   #1, &P6OUT   ; 4 cycles
     jmp     $+2          ; 2 3 cycles
     jmp     L1           ; 2 cycles
        
User's guide (SLAU367P), chapter 4.5.1.5.3: "All jump instructions require 1 code word and take 2 CPU cycles to execute, regardless of whether the jump is take nor not."
        
2) RRAM (probably also RRUM, RRCM, RLAM) takes n-1 cycles in some condition

L2   xor.b   #1, &P6OUT   ; 4 cycles
     rram    #2, R3       ; 2 1 cycle
     jmp     L2           ; 2 cycles

3) CALLA #label or RETA takes 1 cycle less (in some condition)

L3   xor.b   #1, &P6OUT   ; 4 cycles
     calla   #L3x         ; 5+5 9 cycles
     jmp     L3           ; 2 cycles
L3x  reta                 ; = MOVA @SP+, PC (5 cycles)

All tests were done on launchpad with MSP430FR5994 (rev. A), MCLK = 8 MHz, no wait states. The cycles counts have been determined from loop periods which have been measured by a scope.

Best regards,

Tomas

I think Rev A devices are "XMS", i.e. pre-production. You should probably be doing your experiments with Rev C "MSP" devices.

Hi Bruce,

I haven't other launchpad with MSP430FR5994, therefore I have asked for the errata. Does "XMS" mean there can be undocumented bugs?

Thanks.

Tomas

Based on the document history [Ref Errata (SLAZ681M) Sec 8] Errata Rev B was the last one that applied to device Rev A. Errata Rev C ("XMS"->"MSP") fixes maybe 15 prior errata. I have a copy of Errata Rev A, but not Errata Rev B; it doesn't mention anything about instruction timings. (I found a link to SLAZ681B.pdf but it's dead.)

I don't know TI's procedures, but it wouldn't surprise me if the pre-production->production step fixes things that never became formal Errata. As a practical matter, reporting a bug in an "X" device won't get you much attention.

If you buy a (FR5994) Launchpad today, it will have a Rev C device on it. (I have a mixture of RevA and RevC Launchpads.)

Thank you Bruce. I have checked the revision history (section 8 in the errata) and it really looks there was nothing about this issue. I know "XMS" chips are not fully tested and some parameters can be out of specification but TI uses these chips in the official development kits, therefore I think there shouldn't be undocumented bugs if they are known. And it looks this isn't new issue (see old thread "Cycle timing for jump on CPUXV2 chips"). I will replace the MCU and run all tests again. I have primarily tested the DMA and FRAM cache behaviour and this finding is only a side effect.

Tomas

Hi Tomas,

Is your problem solved? Do you still need our support?

Thanks!

Best Regards

Johnson