MSP430F6730: MSP430f673 series chips - frequency configuration problem

Hi,

For Q1 : The related between DCO and MCLK frequency.

As shown in the figure below, DCORSEL is a register that selects the desired clock range in the clock module.These 8 clock frequency ranges have a cross relationship, there are more than one frequency range options, but they will all be locked to the clock frequency set by the user.  Therefore, when selecting the frequency range, you need to select an appropriate frequency range according to the test results in the datasheet to avoid the problem of the clock being unable to stabilize.

Our datasheet gives the fDCO frequency test results (DCORSELx=5, DCOx=0, MODx=0). After enable CS module, the FLL module will adjust the DCO and MOD values according to the user’s settings. You need to refer this two test result : DCORSELx=5, DCOx=0,MODx=0 and DCORSELx=5, DCOx=31,MODx=0, the more rigorous frequency range should be DCORSELx=5, DCOx=0,MODx= 0 between the maximum frequency tested and the minimum frequency tested with DCORSELx=5, DCOx=31, and MODx=0.
For DCORSELx=5, the strict frequency range is: 6.0MHz – 23.7MHz.

For Q2 :  Bit error data.

The internal CS module of F6736 adopts two-level adjustment, DCO and MOD. You can refer to the User Guide for specific adjustment methods and accuracy : https://www.ti.com/lit/pdf/slau208

For Q3 :  How to select DC0X (0~31) and MODx (0~31).

You can found the method that calculate the value in the User Guide : 

You can also refer to this example code : 

https://dev.ti.com/tirex/explore/node?node=AE3hVQ5KblKFE9OakCirWA__IOGqZri__LATEST

Thanks!

Best Regards

Johnson

No one can tell you what the correct values of DCO and MOD are, since this varies by device (along with temperature and voltage).

The way to achieve this is to set DCORSEL=5 [Ref data sheet (SLAS731D) Table 5-10] and set UCSCTL2:FLLN to be 16777216/32768-1 = 511.[Ref User Guide (SLAU208Q) Sec 5.2.6]

The FLL will dynamically adjust DCO and MOD to match the frequency you requested using FLLN. Moreover, it will monitor the frequency and adjust it as conditions (temperature and voltage) change.

The UART error rates are described in User Guide Tables 36-4 and 36-5. They vary by clock and line speed, since they result from an integer divisor.

Example MSP430F673x_UCS_4.c illustrates the procedure for 2.45MHz using a 32kHz crystal.

http://dev.ti.com/tirex/explore/node?node=AMHGg2hEpWELN4xXfipV0g__IOGqZri__LATEST

[Edit: Fixed typo]

[Edit: Johnson He is correct -- DCORSEL=5 (or maybe 6) is a better choice than 7]