Hello
I have 2 questions about the following code which works normally. The purpose of the code is to turn the LED connected to pin 1.0 if the photo resistor connected to the ADC12_A input (pin 6.0) is completely covered, otherwise it turns the LED OFF.
the questions are:
1- what is the default resolution of ADC12_A? According to the datasheet, the resolution is defined using bits ADC12RES in ADC12CTL2 register. It can be either 8, 10, 0r 12. In the following code, ADC12RES=0 which means the resolution is 8 bits, but the resolution is 12 instead of 8?
2- In this code the result of the conversion is available in ADC12MEM0 memory register. Is pin 6.0 connected to this register by default? I thought we need to explicitly configure ADC12MEM0 memory register to read data from one of the ADC12 input pins using ADC12MCTL0 control register. Is my understanding correct?
the code is bellow:
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#include <msp430.h>
int main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
ADC12CTL0 = ADC12SHT00 + ADC12ON; // Sampling time, ADC12 on
ADC12CTL1 = ADC12SHP+ADC12SSEL1; // Use sampling timer+ timer clock is ACLK
ADC12IE = ADC12IE0; // Enable interrupt, you can use 0x01 as well
ADC12CTL0 |= ADC12ENC;
P6SEL |= BIT0; // P6.0 ADC option select
P1DIR |= BIT0; // P1.0 output
P1OUT &= ~BIT0;
while (1)
{
ADC12CTL0 |= ADC12SC; // Start sampling/conversion
__bis_SR_register(LPM0_bits + GIE); // LPM0, ADC12_ISR will force exit
}
}
#pragma vector = ADC12_VECTOR
__interrupt void ADC12_ISR(void)
{
switch(__even_in_range(ADC12IV,34))
{
case 0: break; // Vector 0: No interrupt
case 2: break; // Vector 2: ADC overflow
case 4: break; // Vector 4: ADC timing overflow
case 6: // Vector 6: ADC12IFG0
if (ADC12MEM0 < 0x7ff) // ADC12MEM = A0 < 0.5AVcc?
P1OUT &= ~BIT0; // P1.0 = 1
else
P1OUT |= BIT0; // P1.0 = 0
__bic_SR_register_on_exit(LPM0_bits); // Exit active CPU
case 8: break; // Vector 8: ADC12IFG1
case 10: break; // Vector 10: ADC12IFG2
case 12: break; // Vector 12: ADC12IFG3
case 14: break; // Vector 14: ADC12IFG4
case 16: break; // Vector 16: ADC12IFG5
case 18: break; // Vector 18: ADC12IFG6
case 20: break; // Vector 20: ADC12IFG7
case 22: break; // Vector 22: ADC12IFG8
case 24: break; // Vector 24: ADC12IFG9
case 26: break; // Vector 26: ADC12IFG10
case 28: break; // Vector 28: ADC12IFG11
case 30: break; // Vector 30: ADC12IFG12
case 32: break; // Vector 32: ADC12IFG13
case 34: break; // Vector 34: ADC12IFG14
default: break;
}
}
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Thanks
Mahmoud