Initializing UART A1 for SPI - how?

Chris Shearer Cooper said:

I need to set all four pins

Actually only 3. STE is only required when operatign in multi-master or slave mode. And in slave mode only if there are multiple slaves. In master mode (I won't recomment writing software for an MSP in SPI slave mode unless one has really much experience with the MSP), you don't need this pin.

Chris Shearer Cooper said:

into their "secondary peripheral module function", yes?

Yes. The direction is controlled by the USCI hardware.

PxSEL2 is only available on a few chips where it activates the "Cap sense I/O feature" (turn the pin into an R/C oscillator and routes the result to a timer). On all other MSPs, the SEL2 registers don't exist.

I was confused too when I first read about the PxSEL2 registers in the latest 2x family users guide. I never heard of them at all and didn't find a datasheet in my repository where they are mentioned. It seems you've fallen into the same trap but from the other side :)

Let me tell you what I'm seeing, and then you can hopefully tell me where I'm confused!

I'm looking at theTI datasheet for the MSP430F241x, specifically at the 64-pin package.  Pin 44 is used for "P5.0/UCB1STE/UCA1CLK".  I'm interpreting that to mean this pin has 3 possible functions - {default function}/{primary peripheral module function}/{secondary peripheral module function}.  In order to use pin 44 as UCA1CLK, I have to change port 5.0 to its secondary peripheral module function.

So now looking at the TI document "MSP430x2xx Family User's Guide", page 360, section 8.2.5, it says that to switch a port pin to its secondary peripheral module function, I have to set both PxSEL2 and PxSEL to 1.  If I only set PxSEL to 1, I get the Primary peripheral module function, which for pin 44 is UCB1STE.

So this seems to have nothing to do with "Cap sense", and according to the user's guid, PxSEL2 definitely exists in this entire family.

Confusion!

Thanks,

Chris

 

Hi Chris,

In my opinion, your confusion is totally understandable.  TI's documentation is normally very good, but the SEL2 register thing seems to be lacking.

Anyway, I think both features UCB1STE and UCA1CLK are the primary peripheral module function.  For the '2618, I believe there is no secondary peripheral module function on any pin.  And I believe the SEL2 register is therefore not present. 

So after setting P5SEL bit 0, the pin will function as either UCB1STE or UCA1CLK depending on your configuration of USCI1.  Hence you can deduce the restriction that the A side cannot run in SPI mode at the same time the B side is an SPI 4-wire slave.

Jeff

Indeed, primary and secondary peripheral module function does not refer to the functions listed in the pin assignment. It rather means 'assigned to hardware module 1 or 2 with the same output direction'). And UCA1 and UCB1 are the same hardwar emodule, managing the effective usage internally.

There is currently only one MSP I know of that really has two different peripheral assignments for the same port pin direction (and a PxSEL2 register). And there the secondary usage is the cap sense. All others may have different signals routed to the port pin, but always from the same and managed by the same single hardware module.