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MSP430F2013: SD16 clock speed limitations?

Jonathan Engel
Intellectual 285 points

Part Number: MSP430F2013

When running code on an MSP430F2013 for a sensing application we have firmware that runs at 8MHz using the internal oscillator and calibrated register. However, the datasheet indicates the maximum clock speed for the SD16 module is 1MHz and would require the SMCLK to be divided by 8 when setting up the SD16 module via SD16DIV_3 for example:

SD16CTL = SD16SSEL_1 + SD16REFON + SD16VMIDON + SD16DIV_3

The application sampling rate requires a lower OSR (oversampling ratio) for the SD16 when run at this 1MHz clock speed. The result is that the data converted into SD16MEM0 has a high degree of sample to sample noise, on the order of 250 ADC counts. Simply changing the clock speed to 8MHz (SD16DIV_1) and increasing the OSR by a factor of 2 brings this sample to sample noise down to below 50 ADC counts and the sensing system and algorithm code overall operates much more effectively. Why is the SD16 max clock listed at 1MHz? Why does it work so much better at 8MHz?

  • 0
    TI__Mastermind 40195 points

    Hi,

    I don't know why you increase the OSR, but you can decrease the noise. It doesn't make sense.

    I don't advice you to make SD_16 at 8MHz, because we don't commit about the performance beyond our datasheet. Actually, I don't know the reason. My guess is that the digital circuit delay in the SD_16 doesn't allow it works beyond 1.1MHz. The result is that it may lost data.

    As you are using a OSR =64, that means the same rate is 125kHz. The SNIAD is about 70dB. That means the resolution is about 11bit. If you don't care about the power consumption. I advice you can try to use a SAR ADC as well.

    Eason

  • 0 in reply to Eason Zhou
    Intellectual 285 points

    We're using OSR of 1024, for effective resolution of  about 14 bits at 7kHz sampling. To keep that sample rate at 1MHz we get 128 OSR and a higher amount of sample to sample noise by a factor of 10. For our application the 8MHz clock into SD16 works great but the off-datasheet indication is frowned upon. Is there anyone who can provide the reasoning SD16 clock is limited to 1.1MHz?  

  • 0 in reply to Jonathan Engel
    TI__Mastermind 40195 points

    I think it is come from here:

  • 0 in reply to Eason Zhou
    Intellectual 285 points

    By that logic, since we are using PGA gain = 1x the maximum sampling frequency allowed is a factor of 10x greater than at PGA gain of 32x. If modulator frequency is rated at 1.1MHz at PGA_GAIN=32x then it must be capable of 11MHz at PGA_GAIN=1. True?

  • 0 in reply to Jonathan Engel
    TI__Mastermind 40195 points

    I don't think so, because you also need to take the parasitic capacitance into consideration. Besides, for production, you need to leave some margin for the bad conditions.

    In a word, I don't advice you to use the SD-ADC above spec, because we can't officially commit that the function works well.

    Besides, I consult my colleague, but no one can give me a clear answer why we give 1.1MHz limit.

  • 0 in reply to Eason Zhou
    Intellectual 285 points

    Parasitic beyond the table of sampling capacitance or are you referring to implementation capacitance due to layout, etc?

    You have committed to the fact that 1.1MHz is max modulation freq at Gain=32x based on the settling time info provided. All else being equal, the max modulation freq at Gain=1x should thus be at least 10 times higher. Our testing shows that for our application, the higher OSR enabled with higher modulation freq gives much better performance than holding to the 1.1MHz modulation limit. I guess it is up to us to decide if we are willing to risk working off spec with this part. Thank you for your assistance.

  • 0 in reply to Jonathan Engel
    TI__Mastermind 40195 points

    Yes, some customer would like to take the risk.

    But my advice is that test it on more devices and run for a long time. Actually we don't know what it will be beyond spec. As it is an old device, we have no designer to refer to.

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