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MSP430FR2100: Spy-bi-Wire setup/hold confusion

Ross Petty
Intellectual 300 points
Part Number: MSP430FR2100

I'm reading through the documentation trying to understand the Spy-bi-wire operation. In the MSP430FR2100 datasheet (SLASE78D, Figure 5-15. JTAG Spy-Bi-Wire Timing), it shows that the SBWTDIO setup time starts before the falling edge of the SBWTCK signal, and the hold time ends after the rising edge of the SBWTCK signal (the text agrees with this as well). The diagram shows (and text alludes) that the SBWTDIO is held stable while SBWTCK is low.

However, in the MSP430 programming guide (SLAU320AI, Figure 2-11. Synchronization of TDI and TCLK During Run-Test/Idle) it specifically shows the SBWTDIO changing while SBWTCK is low. The text also describes SBWTDIO needing to change specifically in the low phase of SBWTCK.

So these two pieces of text are contradicting each other. Or have I missed something?

What is the correct behavior/timing needed?

  • 0
    TI__Mastermind 37080 points

    Hi,

    For understand how MSP430 interpret SBW signal, you can refer to:

    Yes, the datasheet will make you think the SBWTDIO is held stable while SBWTCK is low. But actually, it is not. For learning JTAG, I advice you to refer to SLAU320AI.

    You can also find C code example based on MSP432 in slaa754.

  • 0 in reply to Eason Zhou
    Intellectual 300 points

    Thank you: it is important to know that SBWTDIO can change while SBWTCK is low. For good engineering practices, it is still important to understand the setup and hold time requirements to design the interface properly. Is the setup and hold time listed in SLASE78D referring to just the falling edge (instead of both edges, as shown)?

    It would be nice for TI to update this diagram and table to indicate how this actually works, or add a comment about how to properly handle the setup-hold time for the TDI/TCLK portion.

  • 0 in reply to Ross Petty
    TI__Mastermind 37080 points

    Setup time is about falling edge, hold time is about rising edge.

    Thank you for your advice, I will report this to our systems. But this chart is only talking about spec. That is why we write SLAU320AI.

  • 0 in reply to Eason Zhou
    Intellectual 300 points

    But the problem is that SLAU320AI violates the spec:

    If setup starts before the falling edge of SBWTCK and hold ends after the rising edge of SBWTCK, then this diagram shows SBWTDIO changing in the middle of setup and hold time (which is a timing violation).

  • 0 in reply to Ross Petty
    TI__Mastermind 37080 points

    Can you give some explain "SBWTDIO changing in the middle of setup and hold time (which is a timing violation)." 

    Actually see the diagram, the SBWTDIO will not change the voltage between SBWTCLK falling edge and rising edge. Do you mean the SBWTDIO changing time is too long or something else?

  • 0 in reply to Eason Zhou
    Intellectual 300 points

    What do you mean SBWTDIO will not change between SBWTCK falling edge and rising edge??? The diagram clearly shows that it DOES!

  • 0 in reply to Ross Petty
    TI__Mastermind 37080 points

    Sorry it is my mistake. As the picture only talks about TDI slot, I only look at TDI slot not TMS slot.

    If you look at this one, it shows SBWTDIO can change  between SBWTCK falling edge and rising edge, but it talks about TDO slot. I think the key point is that the datasheet doesn't shows where is TDI slot, TMS slot and TDO slot. 

    I think the problem is clear. I will send the  feedback to our system. Anyway, to learn JTAG, I advise you to refer to SLAU320AI.

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