Hi,
How do you change the sampling time in the code below?
boolEUSCI_A_UART_init(uint16_t baseAddress,
EUSCI_A_UART_initParam *param)
{
bool retVal = STATUS_SUCCESS;
//Disable the USCI Module
HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCSWRST;
//Clock source select
HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCSSEL_3;
HWREG16(baseAddress + OFS_UCAxCTLW0) |= param->selectClockSource;
//MSB, LSB select
HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCMSB;
HWREG16(baseAddress + OFS_UCAxCTLW0) |= param->msborLsbFirst;
//UCSPB = 0(1 stop bit) OR 1(2 stop bits)
HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCSPB;
HWREG16(baseAddress + OFS_UCAxCTLW0) |= param->numberofStopBits;
//Parity
switch(param->parity)
{
case EUSCI_A_UART_NO_PARITY:
//No Parity
HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCPEN;
break;
case EUSCI_A_UART_ODD_PARITY:
//Odd Parity
HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCPEN;
HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCPAR;
break;
case EUSCI_A_UART_EVEN_PARITY:
//Even Parity
HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCPEN;
HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCPAR;
break;
}
//BaudRate Control Register
HWREG16(baseAddress + OFS_UCAxBRW) = param->clockPrescalar;
//Modulation Control Register
HWREG16(baseAddress + OFS_UCAxMCTLW) = ((param->secondModReg << 8)
+ (param->firstModReg <<
4) + param->overSampling);
//Asynchronous mode & 8 bit character select & clear mode
HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCSYNC +
UC7BIT +
UCMODE_3
);
//Configure Character length:
HWREG16(baseAddress + OFS_UCAxCTLW0) |= param->bitLength;
//Configure UART mode.
HWREG16(baseAddress + OFS_UCAxCTLW0) |= param->uartMode;
//Reset UCRXIE, UCBRKIE, UCDORM, UCTXADDR, UCTXBRK
HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCRXEIE + UCBRKIE + UCDORM +
UCTXADDR + UCTXBRK
);
return (retVal);
}
