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MSP430FR2676: GPIO Block Diagram

Carter Timm
Prodigy 210 points
Part Number: MSP430FR2676

Greetings,

Does TI make available a block diagram or equivalent circuit for the GPIOs on MSP430FR2676? For example, on a similar part produced by a different vendor, they provide the following diagram:

In particular, I am wondering if reading the actual driven output state of an output port is possible without connecting to another pin set up as an input. Reading the output data register will not suffice because we need the ability to verify what the actual pin state is for our application. In the above example, this is possible as the CMOS output ties directly to the input buffer, which can be enabled even if the pin is in output mode. I was able to find the following from ag_08.pdf (ti.com), which seems to be a very old document and doubt it's relevancy to newer MSP430 models:

Thank you,

Carter

  • 0
    TI__Mastermind 49692 points

    Hi Carter,

    Carter Timm said:
    Does TI make available a block diagram or equivalent circuit for the GPIOs on MSP430FR2676?

    You can find a similar diagram in Section 6.11 Input/Output Diagrams in the MSP430FR2676 datasheet.

    Carter Timm said:
    In particular, I am wondering if reading the actual driven output state of an output port is possible without connecting to another pin set up as an input.

    This is possible. You can easily test it out by running the 'msp430fr267x_1.c' code example. Put a break point in the while(1) loop on Line 81 where the P1OUT bit 0 (P1.0) toggles. In "View" > "Registers", you can check the status of the output by looking at "Port_1_2" > "P1IN". As P1.0 toggles, you should see the "P1IN0" bit toggle as well.

    Hope that helps!

    Regards,

    James

  • 0 in reply to James Evans
    Prodigy 210 points

    Hi James,

    Thanks for the info - I guess I was just Ctrl-F-ing on 'block diagram' and 'schematic' which is why that didn't come up.

    To clarify then, does the Schmitt trigger buffer simply act as a pass-through when not enabled? Seems to me like the Schmitt trigger buffer and output buffer depicted above it cannot be enabled at the same time. Is the "actual" circuitry really more like what I've crudely drawn below? I've always known buffers with enable functionality to go high-impedance if not enabled.

    Thanks again,

    Carter

  • 0 in reply to Carter Timm
    TI__Mastermind 49692 points

    Hi Carter,

    I see what you mean. From what I can tell, the schmitt trigger in the schematic may need an inverter on the enable since the AND gate controlling the output buffer has one. Both of those points are connected to PxSEL.x. When equal to 11, the input and output buffers should be disabled.

    Let me check on this before confirming. I should get an answer in a few days.

    Regards,

    James

  • 0 in reply to James Evans
    Prodigy 210 points

    Hi James,

    Sounds good, thank you for your time.

    Carter

  • 0 in reply to Carter Timm
    TI__Mastermind 49692 points

    Hi Carter,

    Thanks for catching it! I got confirmation today that the current diagram is wrong and will be fixed in a future update. Thanks again!

    Regards,

    James

  • 0 in reply to James Evans
    Prodigy 210 points

    Hi James,

    So just to clarify, the diagram should show an inverted enable on the Schmitt trigger and that's the only change?

    Thanks,

    Carter

  • 0 in reply to Carter Timm
    TI__Mastermind 49692 points

    That's correct.

    Regards,

    James

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