MSP430FR2476: Changing processors and looking for clock set-up help...

Henry Thrun

Part Number: MSP430FR2476
Other Parts Discussed in Thread: MSP430F2132, ,

Hello,

I'm porting over software from an MSP430F2132 to an MSP430FR2476. I'm unable to get the UARTs working (I can't send any data and the interrupts aren't triggering when I receive data). I found this article and started going through it:
https://www.ti.com/lit/an/slaa734a/slaa734a.pdf?ts=1612820504636&ref_url=https%253A%252F%252Fwww.google.com%252F

I got to the point where it suggests checking clock frequencies and I discovered a problem...

Here's what was in the 2132 code for initializing the clock:

// Memory Segment A is valid so initialize DCO with calibrated values
// DCOCTL: Pull DCOx and MODx from CALDCO_1MHZ
// BCSCTL1: Pull RSELx from CALBC1_1MHZ (Also sets XT2OFF=1, XTS=0,
// DIVA=00, XT5V=0)
// BCSCTL2: SELMx=00 (DCOCLK), DIVMx=00 (div1), SELS=0 (DCOCLK),
// DIVXS=00 (div1), DCOR=0 (internal)
DCOCTL = CALDCO_8MHZ;
BCSCTL1 = CALBC1_8MHZ;
BCSCTL2 = 0;

The 2476 has a very different clock structure, based on my understanding of the documentation, so I ended up copying over the CS_init from the OutOfBox_LP-MSP430FR2476 software example and tried adjusting the values to set MCLK and SMCLK to 8MHz. I viewed the clocks with a logic analyzer and they were actually 1.667 to 2.5 MHz. I tried changing the settings back to the example, so now I have:

#define CS_MCLK_DESIRED_FREQUENCY_IN_KHZ 16000 // Target frequency for MCLK in kHz
#define CS_MCLK_FLLREF_RATIO 488 // MCLK/FLLRef Ratio

...

static bool CS_init(void)
{
bool retVal = true;

// Configure one FRAM waitstate as required by the device datasheet for MCLK
// operation beyond 8MHz _before_ configuring the clock system.
FRAMCtl_configureWaitStateControl(FRAMCTL_ACCESS_TIME_CYCLES_1);

//Set DCO FLL reference = REFO
CS_initClockSignal(
CS_FLLREF,
CS_REFOCLK_SELECT,
CS_CLOCK_DIVIDER_1
);

//Set ACLK = REFO
CS_initClockSignal(
CS_ACLK,
CS_REFOCLK_SELECT,
CS_CLOCK_DIVIDER_1
);

CS_initFLLParam param = {0};

//Set Ratio/Desired MCLK Frequency, initialize DCO, save trim values
retVal = CS_initFLLCalculateTrim(
CS_MCLK_DESIRED_FREQUENCY_IN_KHZ,
CS_MCLK_FLLREF_RATIO,
&param
);

//Clear all OSC fault flag
CS_clearAllOscFlagsWithTimeout(1000);

return retVal;
}

I'm expecting 16MHz, but the logic analyzer is showing 1MHz:

When I change the two #defines above, the frequencies change but not to what I expect them...

Is there something else I should be setting? Am I even taking the correct approach based on what was in the original 2132 code?

Thanks in advance for any and all help!

over 4 years ago

0 Leonardo Estevez over 4 years ago

TI__Genius 12615 points

Hi Henry,

I recommend you look at the UART examples for this processor which can be found in the resource explorer here:

https://dev.ti.com/tirex/explore/node?node=AKTwCkgQg9Z0vk0pj8kphQ__IOGqZri__LATEST

BR,
Leo

0 Henry Thrun over 4 years ago in reply to Leonardo Estevez

Prodigy 110 points

Thank you for the link. I tried using msp430fr267x_CS_01.c from the examples which states

// MSP430FR267x Demo - Configure MCLK for 8MHz sourced from DCO.

I took out the pin assignments and the stopping of the WDT because I have that earlier in the code. This is what I have now:

#include <msp430.h>

static void Software_Trim();                // Software Trim to get the best DCOFTRIM value
#define MCLK_FREQ_MHZ 8                     // MCLK = 8MHz

void CS_init(void)
{
    __bis_SR_register(SCG0);                // disable FLL
    CSCTL3 |= SELREF__REFOCLK;              // Set REFO as FLL reference source
    CSCTL1 = DCOFTRIMEN_1 | DCOFTRIM0 | DCOFTRIM1 | DCORSEL_3;// DCOFTRIM=3, DCO Range = 8MHz
    CSCTL2 = FLLD_0 + 243;                  // DCODIV = 8MHz
    __delay_cycles(3);
    __bic_SR_register(SCG0);                // enable FLL
    Software_Trim();                        // Software Trim to get the best DCOFTRIM value


    CSCTL4 = SELMS__DCOCLKDIV | SELA__REFOCLK; // set default REFO(~32768Hz) as ACLK source, ACLK = 32768Hz
                                            // default DCODIV as MCLK and SMCLK source
}

static void Software_Trim()
{
    unsigned int oldDcoTap = 0xffff;
    unsigned int newDcoTap = 0xffff;
    unsigned int newDcoDelta = 0xffff;
    unsigned int bestDcoDelta = 0xffff;
    unsigned int csCtl0Copy = 0;
    unsigned int csCtl1Copy = 0;
    unsigned int csCtl0Read = 0;
    unsigned int csCtl1Read = 0;
    unsigned int dcoFreqTrim = 3;
    unsigned char endLoop = 0;

    do
    {
        CSCTL0 = 0x100;                         // DCO Tap = 256
        do
        {
            CSCTL7 &= ~DCOFFG;                  // Clear DCO fault flag
        }while (CSCTL7 & DCOFFG);               // Test DCO fault flag

        __delay_cycles((unsigned int)3000 * MCLK_FREQ_MHZ);// Wait FLL lock status (FLLUNLOCK) to be stable
                                                           // Suggest to wait 24 cycles of divided FLL reference clock
        while((CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1)) && ((CSCTL7 & DCOFFG) == 0));

        csCtl0Read = CSCTL0;                   // Read CSCTL0
        csCtl1Read = CSCTL1;                   // Read CSCTL1

        oldDcoTap = newDcoTap;                 // Record DCOTAP value of last time
        newDcoTap = csCtl0Read & 0x01ff;       // Get DCOTAP value of this time
        dcoFreqTrim = (csCtl1Read & 0x0070)>>4;// Get DCOFTRIM value

        if(newDcoTap < 256)                    // DCOTAP < 256
        {
            newDcoDelta = 256 - newDcoTap;     // Delta value between DCPTAP and 256
            if((oldDcoTap != 0xffff) && (oldDcoTap >= 256)) // DCOTAP cross 256
                endLoop = 1;                   // Stop while loop
            else
            {
                dcoFreqTrim--;
                CSCTL1 = (csCtl1Read & (~DCOFTRIM)) | (dcoFreqTrim<<4);
            }
        }
        else                                   // DCOTAP >= 256
        {
            newDcoDelta = newDcoTap - 256;     // Delta value between DCPTAP and 256
            if(oldDcoTap < 256)                // DCOTAP cross 256
                endLoop = 1;                   // Stop while loop
            else
            {
                dcoFreqTrim++;
                CSCTL1 = (csCtl1Read & (~DCOFTRIM)) | (dcoFreqTrim<<4);
            }
        }

        if(newDcoDelta < bestDcoDelta)         // Record DCOTAP closest to 256
        {
            csCtl0Copy = csCtl0Read;
            csCtl1Copy = csCtl1Read;
            bestDcoDelta = newDcoDelta;
        }

    }while(endLoop == 0);                      // Poll until endLoop == 1

    CSCTL0 = csCtl0Copy;                       // Reload locked DCOTAP
    CSCTL1 = csCtl1Copy;                       // Reload locked DCOFTRIM
    while(CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1)); // Poll until FLL is locked
}

Unfortunately my MCLK and SMCLK look the same as before, 1.667 to 2.5MHz with a lot of jitter. Also, my ACLK has been 32.89 kHz...

I noticed the file's name includes MSP430FR267x but it's in the MSP430FR2476 folder, so I gather that it should be compatible...

Is there anything else I can try? Thanks...

0 Leonardo Estevez over 4 years ago in reply to Henry Thrun

TI__Genius 12615 points

Hi Henry,

Is it possible that your logic probe is sampling at a frequency which is less than 2 * 8Mhz and that you are seeing aliasing issues? Can you confirm at what frequency you are sampling?

BR,
Leo

0 Henry Thrun over 4 years ago in reply to Leonardo Estevez

Prodigy 110 points

Hi Leo,

I just happened to have thought to check this as well. I was indeed only sampling at 5MS/s. I turned off some channels and was able to increase it. The clocks are running at 8MHz as expected.

Thank you so much for your help!

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MSP430FR2476: Changing processors and looking for clock set-up help...