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MSP430FR6989: Using external square wave generator for clock

tunguskar
Intellectual 440 points

Part Number: MSP430FR6989

Hi, 

I want to drive the high frequency part of the chip with an external square wave generator at 8MHz. External crystal for LFXT is connected. The Version before with an external LFXT and the internal DCO worked. 

The 8MHz signal looks like this:

Now the initialization:

  • PJSEL1 &= ~(BIT4 + BIT5 + BIT6);
    PJSEL0 |= BIT4 + BIT5 + BIT6;
  • Than is the LF crystal initialized, which worked before

  • CSCTL4_bitfield.HFXTOFF_bit = 1;

    CSCTL4_bitfield.HFXTBYPASS_bit = 1; //  enable bypass
    CSCTL4_bitfield.HFXTDRIVE_bits = 0;  // low drive mode
    CSCTL4_bitfield.HFFREQ_bits = 1;        // 4 to 8MHz
    CSCTL5_bitfield.ENSTFCNT2_bit = 1;
    SFRIEx_bitfield.OFIE_bit = 0;
    CSCTL4_bitfield.HFXTOFF_bit = 0;

    do
    {
         CSCTL5_bitfield.HFXTOFFG_bit = 0;
         SFRIFGx_bitfield.OFIFG_bit = 0;   

          if (exitCount >= CLOCKGENERAL_HFXT_ERROR_COUNT)
          {
                CSCTL4_bitfield.HFXTOFF_bit = 1;
                return clockGeneral_status_error;
           }
           exitCount++;

    } while (SFRIFGx_bitfield.OFIFG_bit);

  • Than set CDCTL2_bitfield.SELM = 5; // HFXT
  • Than set CDCTL2_bitfield.SELS = 5; // HFXT

system runs but not really correctly

  • 0
    TI__Mastermind 49692 points

    Hello,

    I suspect your issue is caused by configuring the clock setting registers without unlocking them first. See how this is done in the msp430fr69xx_cs_04.c code example found in TI Resource Explorer. Also, you're referring to LFXT but you're actually trying to use HFXT.

    Regards,

    James

  • 0 in reply to James Evans
    Intellectual 440 points

    Hi James,

    Sorry I gave just a snippet from the HFXT init before the LFXT init is done.

    I did the unlock before.

    Steps are:

    - CSCTL0.CSKEY_HighByte = 0xA5; //unlock clock peripheral

    - configure LFXT (External 32 KHz)

    - configure HFXT (External square wave generator 8MHz)

    - CSCTL1 = 12; //8MHz

    - CSCTL2.SELM = 5; //MCLK source HFXT

    - CSCTL3.DIVM = 0; //MCLK divider 1

    - CSCTL2.SELS = 5; //SMCLK source HFXT

    - CSCTL3.DIVS = 1; // SMCLK divider 2

    - CSCTL4.SMCLKOFF = 0; // Activate SMCLK

    - CSCTL2.SELA = 0; //Clock Source LFXT

    - CSCTL3.DIVA = 0; // Divide by 1

    - CSCTL0.CSKEY_HighByte = 0; //lock the clock peripheral

  • 0
    Intellectual 440 points

    I did a morre simple setup: (even this does not work)

    PJSEL1 &= ~(BIT4 + BIT5 + BIT6 + BIT7);
    PJSEL0 |= BIT4 + BIT5 + BIT6 + BIT7;

    PM5CTL0 &= ~LOCKLPM5;

    CSCTL0_H = CSKEY >> 8; // Unlock CS registers
    CSCTL2 = SELA__LFXTCLK | SELS__HFXTCLK | SELM__HFXTCLK; // set all sources
    CSCTL3 = DIVA__1 | DIVS__2 | DIVM__1; // Aclk divider 1, SMCLK divider 2 = 4MHz, MCLK divider = 1 = 8MHz
    CSCTL4 |= LFXTDRIVE_3 | HFXTBYPASS | HFFREQ_1;; //drive ACLK and bypass SMCLK becaus it is driven from square generator
    CSCTL4 &= ~(LFXTOFF | HFXTOFF | SMCLKOFF); // release all clocks
    do
    {
    CSCTL5 &= ~(LFXTOFFG | HFXTOFFG); // Clear XT1 and XT2 fault flag
    SFRIFG1 &= ~OFIFG;
    }while (SFRIFG1&OFIFG); // Test oscillator fault flag
    CSCTL0_H = 0; // Lock CS registers

  • 0
    TI__Mastermind 49692 points

    Hello,

    That 8 MHz signal looks fairly noisy.

    Are you applying the square wave to the HFXIN pin? The HFXOUT pin is just configured as a GPIO in this mode. I would also focus on HFXT for now and would recommend using the internal VLO for ACLK until you get the HFXT working. Then, you can add the code to use LFXT.

    Are you seeing an oscillator fault flag that can't be cleared? You could also try outputting SMCLK or MCLK and capture it with an oscilloscope.

    Regards,

    James

  • +1 in reply to James Evans
    Intellectual 440 points

    Hi James,

    Works now. The problem was, I swaped the HFXIN and HFXOUT pin. 

    Thanks for your recommondation to remove the Setting for HFXOUT Pin. I removed it. I thought I saw it in the sample code the TI source library.

    Jus for sure I place the code for initialization of this topic now. Maybe anybody can use it:

    PJSEL1 &= ~(BIT4 + BIT5 + BIT6);
    PJSEL0 |= BIT4 + BIT5 + BIT6;

    PM5CTL0 &= ~LOCKLPM5;

    CSCTL0_H = CSKEY >> 8; // Unlock CS registers
    CSCTL2 = SELA__LFXTCLK | SELS__HFXTCLK | SELM__HFXTCLK; // set all sources
    CSCTL3 = DIVA__1 | DIVS__2 | DIVM__1; // Aclk divider 1, SMCLK divider 2 = 4MHz, MCLK divider = 1 = 8MHz
    uint16_t temp = CSCTL4;
    temp |= HFXTDRIVE_0 | HFXTBYPASS | HFFREQ_1 | LFXTDRIVE_3;
    CSCTL4 = temp ; //drive ACLK and bypass SMCLK becaus it is driven from square generator
    CSCTL4 &= ~(LFXTOFF | HFXTOFF | SMCLKOFF); // release all clocks
    do
    {
    CSCTL5 &= ~(LFXTOFFG | HFXTOFFG); // Clear XT1 and XT2 fault flag
    SFRIFG1 &= ~OFIFG;
    }while (SFRIFG1&OFIFG); // Test oscillator fault flag
    CSCTL0_H = 0; // Lock CS registers

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