Part Number: MSP430G2553
Other Parts Discussed in Thread: MSP430FR2676
Hi,
Good day.
Our customer is using the MSP430G2553 and they have the question below. We would appreciate your help on this matter.
"I have a question about the gate time for the capacitance measurement application. I am using the Pin Oscillator method (i.e., RO_PINOSC_TA0_WDTp).
In SLAA574, page 18, section 4.2, you write: "For the RO method, having a high gate clock frequency increases power consumption during electrode scan. If possible, combinations with lower clock frequencies and higher
accumulation cycles are preferred.". So, I would say that the best settings for low power application include the lowest possible operating frequency and the highest accumulation cycle value (i.e., 8192 for watchdog implementation as gate time).
In SLAA515B, page 8, subsection 4.2.3, you write: "Increasing the frequency of SMCLK and decreasing the
WDTp_GATE_NUMBER, for example, changes it from WDTp_GATE_8192 to WDTp_GATE_512 and
reduces the gate time as well as the power consumption.". Here, I would say that a higher frequency combined with the lowest accumulation cycle value is preferred for low power consumption.
At this point, I am perplexed, and maybe I am missing something. It seems to me that these two documents contrast each other. My goal is to obtain the lowest possible consumption, and I am already using the ACLK to source the WTD+ with a frequency of around 1.5 kHz (I am using the VLO as a clock source), but I cannot understand what is best: high or low accumulation cycles?"
Looking forward to your inputs.Thank you.
Regards,
Cedrick
