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MSP430F6736A: System Clock fine tuning

Part Number: MSP430F6736A
Other Parts Discussed in Thread: MSP430WARE

Hi,

 

I'm using Msp430F6736A in a project and generating 25.165Mhz clock as system clock

I enabled that clock on PJ_1/MCLK/TDI/TCLK using

PJSEL=BIT1;
PJDIR=BIT1; 

When I measure that clock using Oscilloscope I observer discrepancy in clock i.e. there is noise or the clock is not stable . The discrepancy is upto 600hz 

Is there a way to fine tune this or trim this clock ?

Thank You 

  • Hello,

    I couldn't find a 25 MHz code example for the F6736A, but I did find the 'MSP430F55xx_UCS_10.c' example for the F55xx family that should work on the F6736A. You'll need to change the pins that output the clocks though. More importantly, this example demonstrates how to properly increase the VCORE settings level by level. If you have MSP430Ware installed in CCS, then you can find the same example there and import it into your workspace.

    Regards,

    James

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