Part Number: MSP430F6736A
Other Parts Discussed in Thread: MSP430WARE
Hi,
I'm using Msp430F6736A in a project and generating 25.165Mhz clock as system clock
I enabled that clock on PJ_1/MCLK/TDI/TCLK using
PJSEL=BIT1;
PJDIR=BIT1;
When I measure that clock using Oscilloscope I observer discrepancy in clock i.e. there is noise or the clock is not stable . The discrepancy is upto 600hz
Is there a way to fine tune this or trim this clock ?
Thank You