MSP430FR5969: Field firmware upgrade of multiple MSP430s

I made MSP-GANG like SBW master device, and started with slau320, because at that time this one was only open source project. Today, all TI FET's firmware (MSP Debug Stack) is open source (and with less bugs compared to slau320).

My target was to support all MSP SBW devices, so it is more complex than yours. Each target device must have own / not shared / separated SBW DATA / CLK lines. Also, with only FRAM targets, things become more simple, because there is no flash memory problems. Everything can be done by using Quick Read / Write functions. There is also mailbox system, that can be used to exchange data between SBW master and free running target(s). However, it is not one-week job, for sure.

Total number of target devices in your system is irrelevant, if you want to update one by one, not in parallel. But I don't see problem even if you want to do it in parallel. If there is capacitor on target device RESET (SBW data) pin than take care about signal shape and pin (total) current during switching. I used system with 8 target device (master pin number / current / something else  limitation). My SBW master device was connected to PC by USB, and CLI was used on PC (Win / Linux / OSX) side,,,

D:\>flash -f test_msp430f5510.txt -e -w -v -crcr -mrr

File: "test_msp430f5510.txt"
@8000 32768 bytes
Total Size: 32768 bytes

Found SBW+ at COM4

Get Device
# JTID Fuse Device Core Hard Soft LotWafer DieX DieY
0  91   OK   3081  2106  10   10  B7A50951 0A00 1100
1  91   OK   3180  1104  12   12  013BB046 0D00 1E00
2  91   OK   5435  0100  10   10  ADE98146 0400 2000
3  91   OK   3180  1104  12   12  013BB046 1200 1E00
4  91   OK   3080  1104  30   10  B15B9446 2000 1700
5  91   OK   3180  1104  12   12  34449346 2200 3600
6  91   OK   3881  1106  10   10  219CA446 1800 0F00
7  91   OK   3180  1104  12   12  013BB046 2700 2E00

Erase

Write
Time: 423 ms  Speed: 75.7 KB/s

Verify
Time: 159 ms  Speed: 201.3 KB/s

CRC Rev
File  #0   #1   #2   #3   #4   #5   #6   #7 
C841 C841 C841 C841 C841 C841 C841 C841 C841
Time: 40 ms  Speed: 800.0 KB/s

Marginal Read Rev
Mode File  #0   #1   #2   #3   #4   #5   #6   #7 
  0  C841 C841 C841 C841 C841 C841 C841 C841 C841
  1  C841 C841 C841 C841 C841 C841 C841 C841 C841
Time: 460 ms  Speed: 69.6 KB/s

Release Device

Total Time: 1268 ms

Thanks zrno soli for sharing the details of your system and the reference to MSP Debug Stack, it's very helpful.  After digging deeper, the approach I'd like to take is to build a variant version of an ezFET Lite that runs on the master in our system.  It would only need to load firmware on the targets, and hopefully this would involve only Quick Writes (no Quick Reads) and thereby avoid contention on TDIO.   So there would be no FRAM write verification.    Our system is using FRAM devices (FR5969 and FR5994), and we have one master with USB-UART bridge to connect to host.  However the SBW pins of the master and targets are common (shared) lines, and using separate lines to each of ~128 targets is not an option due to PCB routing constraints.   Does this Quick-write only approach sound feasible?

Unfortunately, this (shared TDIO) is not possible. Any SBW shift operation (in Quick Read / Write / whatever) will have multiple combination of 2 bits out (master TDIO write, slave TDIO read) followed by one bit in (slave TDIO write, master TDIO read). You can see this in slau320 pictures. So, when all target devices respond and write one bit, some of them will be high, and others low, resulting in short circuit, and target reset.

In first MSP-GANG version (you can see this in part of schematic in some TI document) TCLK line (for six targets) is shared between all target devices. I don't like this, but it can work. TDIO is not shared, each target device use separate one.

And SBW don't support chaining, so it is not possible to use target devices in serial connection. Only parallel.