Part Number: MSP430F5438A
In MSP430F5438A controller:
while One of the unused Bank erase initiated, controller not able do the normal execution(unpredictable behavior) from other banks of flash or RAM.
is this expected in MSP430F5438A controller?
The bank erase code is as follows:
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/* Clear Lock bit */
((FCR *)FLASH_BASE)->FCTL3 = FWKEY;
while (true == flash_busy_status());
/* FLASH34 errata: no concurrent access to flash bank while erasing */
/* Get the interrupt state status */
interrupt_state = get_interrupt_state();
/* Disable the interrupts */
disable_interrupts();
/* Due to architecture issue a NOP before processing ahead */
NOP();
/* Set MERAS bit */
((FCR *)FLASH_BASE)->FCTL1 = FWKEY + MERAS;
/* Write a dummy value to flash pointer to start the erase */
*flash_ptr = 0U;
/* test busy */
/* We cannot test for BUSY flash since it will put the controller in hold
* as it will take 23-32 msec for bank erase.*/
enable_interrupts();
/* Clear MERAS bit */
((FCR *)FLASH_BASE)->FCTL1 = FWKEY;
/* Set LOCK bit */
((FCR *)FLASH_BASE)->FCTL3 = FWKEY + LOCK;
