MSP430F2272: I2C Master receive START condition continuously triggers TX ISR

Hello MSP430 Forum.

As told on the title, after a START condition, when MSP is in MASTER mode and receiving a message from slave, the code execution keeps entering the TX ISR, even the TX interrupt is disabled (IE2 == UCB0RXIE). When in master mode and TRANSMINTTING a message, everything works fine!

On the master side there's a MSP430F2272 and on the slave side there's a SHT30-DIS.

Here goes pieces of my code:

//-----------------------------------------------------------------------
// PORT3 configuration
//
P3REN       &= ~(I2C_SDA | I2C_SCL);    //I2C_SDA == 0x02, I2C_SCL == 0x04
P3DIR       |=  (I2C_SCL);
P3SEL       |=  (I2C_SDA | I2C_SCL);

//-----------------------------------------------------------------------
// I2C configuration
//
UCB0I2CSA = SHT3X_I2C_ADDRESS;      // I2C slave Address.  The I2CSAx bits contain the slave address of the    ;
UCB0CTL1 |= UCTR;                   // UCTR=1 => Transmit Mode (R/W bit = 0)
IFG2 &= ~(UCB0TXIFG | UCB0RXIFG);   // Clear Interrupt flags
IE2 &= ~UCB0RXIE;                   // disable Receive ready interrupt
IE2 |= UCB0TXIE;                    // enable Transmit ready interrupt

//-----------------------------------------------------------------------
// Send Measurement command to slave device
//
//Send START condition
UCB0CTL1 |= UCTXSTT;                        // Send start. Transmit START condition in master mode.
__delay_cycles(5);

//Send MSB
IFG2 &= ~UCB0TXIFG;
UCB0TXBUF = SHT3X_MEAS_TEMP_MSB;            // Send MSB to device
__bis_SR_register(LPM3_bits + GIE);         // Wait till Tx interrupt occur

//Send LSB
IFG2 &= ~UCB0TXIFG;
UCB0TXBUF = SHT3X_MEAS_TEMP_LSB;            // Send LSB to device
__bis_SR_register(LPM3_bits + GIE);         // Wait till Tx interrupt occur

//Send STOP condition
UCB0CTL1 |= UCTXSTP;                        // Send STOP condition to slave knows that data transfer ended
while((UCB0CTL1 & UCTXSTP));                // 2 ensure STOP was send

//Put Master in RECEIVE status
UCB0CTL1 &= ~UCTR;                          // UCTR=0 => Receive Mode (R/W bit = 1)
IFG2 &= ~(UCB0RXIFG | UCB0TXIFG);           //UCB0RXIFG is set when UCB0RXBUF has received a complete character
IE2 &= ~(UCB0TXIE);                         // disable Transmit ready interrupt
IE2 |= UCB0RXIE;                             // enable Receive ready interrupt

//Send START condition to slave send data
//Slave clock streching is enabled
UCB0CTL1 |= UCTXSTT;                        // Send start. Transmit START condition in master mode.
__delay_cycles(5);

//Just a loop 2 know when NACK & STOP should be sent
for(i=BYTES2RECEIVE; i > 0; i--)
{
    __bis_SR_register(LPM3_bits + GIE);

    if(!(i-1))
    {
        UCB0CTL1 |= UCTXNACK;               // Send NACK condition
        __delay_cycles(5);
        UCB0CTL1 |= UCTXSTP;                // Send STOP condition to slave knows that data transfer ended
        while((UCB0CTL1 & UCTXSTP));
    }
}

//TRANSMIT ISR
#pragma vector=USCIAB0TX_VECTOR
__interrupt void USCIABTX_ISR(void)
{
    if((IFG2 & UCA0TXIFG))
        IFG2 &= ~UCA0TXIFG;
    if((IFG2 & UCB0TXIFG))
        IFG2 &= ~UCB0TXIFG;
    __bic_SR_register_on_exit(LPM3_bits); // EXIT LPM3

}

//RECEIVE ISR

#pragma vector=USCIAB0RX_VECTOR
__interrupt void USCIABRX_ISR(void)
{
    if((IFG2 & UCB0RXIFG))
    {
        RXData[i-1] = UCB0RXBUF;             // Get RX data
        IFG2 &= ~UCB0RXIFG;
    }
    __bic_SR_register_on_exit(LPM3_bits);    // Exit LPM3
}

I'm able to see the data that should be sent and received to and from slave on oscilloscope. Everything is fine, except my program keeps entering and exiting the TX ISR. When I pause program execution and disable RX interrupt, no TX ISR entering occurs.

Any ideas??

Thanks in advance!