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EK-TM4C123GXL: How to set up clock Frequency for UART communication in UART_CC_R?

Part Number: EK-TM4C123GXL

I need to set up  clock frequency of 33.3MHz and set a Baud Rate of 9600 using UART0.

My SYSCLK is on 40 Mhz.

As UART_CC_R has only 4 bits to RW I'm not sure how can a value be assigned in UART_CC_R?

Thanks in advance.

  • Hi,

      The UART_CC is a register to select the clock source for the UART module. It is not a divisor. Below is the excerpt from the datasheet. 

    By default it is selecting the SYSCLK as the clock source. You said you have already configured your system clock to be 40MHz. What you need to is divide the SYSCLK to proper baud rate using UARTIBRD and UARTFBRT registers.

    Please note we do not support DRM (direct register manipulation) style of coding. If you need to use DRM then please look at how the API implements the code to configure the UART baud rate. The API to use will be  UARTConfigSetExpClk. Below is an example to configure the UART with 115200 baud rate. 

    //
    // Configure the UART for 115,200, 8-N-1 operation.
    //
    UARTConfigSetExpClk(UART0_BASE, ROM_SysCtlClockGet(), 115200,
    (UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE |
    UART_CONFIG_PAR_NONE));

    Here is the source code you can find the TivaWare driver library. 

    void
    UARTConfigSetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk,
                        uint32_t ui32Baud, uint32_t ui32Config)
    {
        uint32_t ui32Div;
    
        //
        // Check the arguments.
        //
        ASSERT(_UARTBaseValid(ui32Base));
        ASSERT(ui32Baud != 0);
        ASSERT(ui32UARTClk >= (ui32Baud * UART_CLK_DIVIDER));
    
        //
        // Stop the UART.
        //
        UARTDisable(ui32Base);
    
        //
        // Is the required baud rate greater than the maximum rate supported
        // without the use of high speed mode?
        //
        if((ui32Baud * 16) > ui32UARTClk)
        {
            //
            // Enable high speed mode.
            //
            HWREG(ui32Base + UART_O_CTL) |= UART_CTL_HSE;
    
            //
            // Half the supplied baud rate to compensate for enabling high speed
            // mode.  This allows the following code to be common to both cases.
            //
            ui32Baud /= 2;
        }
        else
        {
            //
            // Disable high speed mode.
            //
            HWREG(ui32Base + UART_O_CTL) &= ~(UART_CTL_HSE);
        }
    
        //
        // Compute the fractional baud rate divider.
        //
        ui32Div = (((ui32UARTClk * 8) / ui32Baud) + 1) / 2;
    
        //
        // Set the baud rate.
        //
        HWREG(ui32Base + UART_O_IBRD) = ui32Div / 64;
        HWREG(ui32Base + UART_O_FBRD) = ui32Div % 64;
    
        //
        // Set parity, data length, and number of stop bits.
        //
        HWREG(ui32Base + UART_O_LCRH) = ui32Config;
    
        //
        // Clear the flags register.
        //
        HWREG(ui32Base + UART_O_FR) = 0;
    
        //
        // Start the UART.
        //
        UARTEnable(ui32Base);
    }

  • Monday morning greetings & wonderful/caring detail here (w/in your posting) - Charles!

    Indeed - poster has wandered (or been directed ... i.e. 'pushed') down the (dreaded) 'DRM' path.     (he should step gingerly over/around the 'broken bodies' - loitering this worn trail...)    And - may it be asked - from where did those (now) very worn/piled, ground-stained 'Job Security Now' signs emanate?

    Staff (et moi) are curious:

    • he mentions a 40MHz SysClk and (even) earlier - a  33.3MHz 'clock frequency' - yet fails to note its name & purpose!   His revelation of (that)  33.3MHz clock's role would prove of interest.
    • our firm has a 'Stack of Vegas chips' on his desire being (additionally) to 'Change SysClk' from 40MHz to 33.3MHz - which is achieved (again best) via the API's:

    SysCtlClockSet() with the parameters:

    •  SYSCTL_USE_PLL 

    OR'ed with

    •  SYSCTL_SYSDIV_6   (200MHz / 6 = 33.33MHz)

    Such achieves his (not  too  clearly stated)  33.3MHz, 2nd goal...

    Tag: Use of the API speeds & eases device programming - yet demands awareness of the API's presence!    (it appears that poster was 'minimally or even unaware' of the API...)