Amplification on Sysctl #16

Robert Adsett

Rather image heavy, but I think that may prove useful.

We've been checking our power supply to see if we may be running afoul of the SYSCTL #16 errata. The wording on the errata is somewhat opaque and we are not sure we understand it.

The bottom image is a scope capture and shows a overshoot, presumably as the LDO switches on). The second image from the bottom shows a zoom-in of that section illustrating a peak of around 75mV, compared to 75 to 100uS later.

I think I would interpret this as being a risk for SYSCTL #16 but It's not entirely clear. I also would have expected there might be some bounds on the magnitude of the difference but that's not mentioned in the errata either.

Any thoughts Amit?

On a related note, the parts I see lately have E6PMI on the second line. The errata indicates there should be a revision indicator on the end which I am not seeing. Is the revision indicated elsewhere on the package?

Robert

I'm not hanging around for an answer so don't take time away to deal with it until after the weekend.

over 9 years ago

0 Amit Ashara over 9 years ago

TI__Guru**** 244400 points

Hello Robert

If this is on TM4C129 rev-3 (A2 revision silicon), then it does not have an effect. But if this is something on the TM4C129 rev-1 or rev-2 signal, then what you may see is that the LDO may power up briefly and then go back to 0V

Regards,
Amit

0 Robert Adsett72 over 9 years ago in reply to Amit Ashara

Guru 10570 points

Silly me, I thought I'd included the chip. It's a 4C1230. Sorry about that.

The errata states it applies to rev 6 and 7 silicon. I do have an older board on my desk marked as rev 6 on the package of the ic stuffed. A newer ic does not have a revision marked

Robert

0 Amit Ashara over 9 years ago in reply to Robert Adsett72

TI__Guru**** 244400 points

Hello Robert

OK. It does apply for the TM4C123x device in that case irrespective of the revision.

As for the issue itself, it has a small window of failure (I believe it is few 10's of mV in a window of 200-300ns) w.r.t to the non-monotonicity of the supply ramp. However if the ramp is monotonic or runs into a large window of few us, then the failure may not show up.

Regards
Amit

0 Robert Adsett72 over 9 years ago in reply to Amit Ashara

Guru 10570 points

Thanks Amit, I'm not sure I'm enlightened. I may be back with further questions.

Robert

0 Amit Ashara over 9 years ago in reply to Robert Adsett72

TI__Guru**** 244400 points

Hello Robert,

I do understand, the issue is slightly more complicated than my 2 lines on the issue.

For some strange reason a second post on the same topic arrived on the forum.

e2e.ti.com/.../473066

Regards
Amit

0 Robert Adsett over 9 years ago in reply to Amit Ashara

Guru 27665 points

As per discussions in e2e.ti.com/.../473066 I started varying clock frequency, first by removing the clock setup so it stayed with the default clocking.

I wasn't seeing any real measurable change and then realised the device will be held in reset until the supply voltage reaches 3V04 (external supply supervisor) so the entire glitch happens while the device is in reset. Configuration cannot help.

Robert

0 Amit Ashara over 9 years ago in reply to Robert Adsett

TI__Guru**** 244400 points

Hello Robert,

Yes. The other way of seeing it is to monitor the VDDC which shall power up briefly before decaying via the VDDC caps to 0. You would need to slow down the ramp around the VDDS Trip Point.

Regards
Amit

0 Robert Adsett over 9 years ago in reply to Amit Ashara

Guru 27665 points

Sorry Amit, I'm not understanding your point.

I cannot slow down the micro's current draw at that point, it's entirely internal and the micro is in reset. Reducing the current available from the DC/DC would surely make matters worse not better.

Robert

0 Amit Ashara over 9 years ago in reply to Robert Adsett

TI__Guru**** 244400 points

Hello Robert,

I was referring to the method to reproduce the issue, by changing the voltage ramp profile.

Regards
Amit

0 Robert Adsett over 9 years ago in reply to Amit Ashara

Guru 27665 points

Ah, I'm trying to get rid of the glitch, thus my note that the device is in reset and therefore modifying the clock configuration in SW will have no effect.

Robert

0 Amit Ashara over 9 years ago in reply to Robert Adsett

TI__Guru**** 244400 points

Hello Robert,

That glitch is generated when the internal LDO start's up and as you said, the system is still under reset.

Regards
Amit

0 Robert Adsett over 9 years ago in reply to Amit Ashara

Guru 27665 points

Amit Ashara said:
However if the ramp is monotonic or runs into a large window of few us, then the failure may not show up.

Amit, I did say I wasn't sure this clarified matters and we've been puzzling over this here.

It suggests that if there is a dip that runs for a long period the problem is less likely to appear. Is that what you meant to indicate?

Robert

I think the wording of this particular errata needs to be re-worked for clarity.

0 Amit Ashara over 9 years ago in reply to Robert Adsett

TI__Guru**** 244400 points

Hello Robert,

Yes, in case of a monotonic ramp or if the glitch does occur but it is of wide width then it would not occur.

But under scope, it was very tough to see the issue when the failure occurs as captures were intermittent on the issue and too much noise or LDO startup distorted the capture. Hence we reverted to analog sims to ascertain under ideal conditions.

Regards
Amit

0 Robert Adsett over 9 years ago in reply to Amit Ashara

Guru 27665 points

Excellent, Thanks Amit.

Robert

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Amplification on Sysctl #16